Matsushita Electric Industrial Co., Ltd.

Keisuke Kaneko

Nobuo Higaki

Masato Suzuki

Shinji Ozaki

Toru Morikawa

Satoshi Ogura

In an information processing device including a processing circuit that performs processing in synchronization with a clock, and a clock supply control circuit that controls supply of the clock to the processing circuit, the number of cycles required from start of execution of processing in the processing circuit until output of a result of the processing is extracted, the extracted number of cycles is transferred to the clock supply control circuit, the supply of the clock is started when the processing is started in the processing circuit, and the supply of the clock to the processing circuit is stopped when the supply of the clock with the number of cycles is completed. Thus, a clock control method and an information processing device employing the clock control method are provided that allow power consumption to be reduced without impairing an execution efficiency of pipeline processing.

Clock control method and information processing device employing the clock control method

A first instruction requiring that a data word should be read out from a data memory and be stored in a certain register in a register set, and then a second instruction requiring that two operands, respectively read out from the register and another register in the register set, should be added are pipeline-processed. In a high-speed mode in which an operation clock having a higher frequency is supplied, a data cache intervened between an instruction execution circuit and the data memory is controlled to supply a data word to a WB (write back) stage of the instruction execution circuit within two cycles with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is supplied from the WB stage to an EX (operation execution) stage of the instruction execution circuit. In a low-speed mode in which an operation clock having a lower frequency is supplied, the data cache is controlled to supply a data word to an MEM (memory access) stage of the instruction execution circuit within one cycle with respect to an input address associated with the first instruction. In order to execute the second instruction, the data word is bypassed from the MEM stage to the EX stage.

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Yawata, Japan

Keisuke Kaneko