Panasonic Corporation

Keisuke Kaneko

Tetsuya Tanaka

Ryuta Nakanishi

Hazuki Okabayashi

Masaitsu Nakajima

Takao Yamamoto

Tokuzo Kiyohara

A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.

Parallel caches operating in exclusive address ranges

A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.

Cache memory system, and control method therefor

An object of the present invention is to reduce power consumption accompanying a cache hit/miss determination. To achieve this object, when accessing a cache memory provided with a means for setting whether a cache refill to each way in the cache memory is allowed for each CPU or each thread, first, a first cache hit/miss determination is performed only on the way for which a refill is set to be allowed (Steps-and-), and if the first cache hit/miss determination results in a cache hit, the access is ended (Step-). In the case of a cache miss, the way for which a refill is not set to be allowed is accessed (Step-), or a second hit/miss determination is performed by accessing all the ways (Step-).

Cache memory control method and cache memory control device

The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.

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Kyoto, Japan

Keisuke Kaneko