Mitsubishi Denki Kabushiki Kaisha

Mitsubishi Denki Kabushiki

Keishi Murakami

Fumio Ishizu

Hiroshi Kubo

Akinori Taira

Kazuo Tanada

Yasushi Sogabe

Takayuki Nagayasu

Kouji Ueda

In a data transmission system, a transmitter adds control data to transmission data, and modulates the resultant signal by a predetermined modulation method, and sends the result in a wireless manner. A receiver detects a reception power intensity by use of the control data contained in the transmitted signal. A random pattern is used for a reception-power detecting portion for detecting a reception power intensity, which is contained in the control data.

Data transmission system, data transmitter and data receiver used in the data transmission system

In a sequence estimation method and a sequence estimator of the present invention, a metric is calculated using a received signal and its estimated value, also another metric is calculated using a filtering result via a matching filter, one of these metrics is selected based on a characteristic of the channel or these metrics are combined, when a transmitted signal sequence transmitted from a transmission side is estimated based on a characteristic of a received signal and a channel using a list output Viterbi algorithm for deciding one or a plurality of survivors for each state of the Viterbi algorithm including one or more states. The operation speed and the characteristic of a channel can be improved using the smallest circuit scale even if the characteristic of a channel has a long delay time, in a sequence estimation method and a sequence estimator.

Sequence estimation method and sequence estimator

A demodulator is constituted by: a clock recovery circuit for generating a recovered clock from the series of received data and outputting the recovered clock; a state estimation circuit for making an estimation about a reception state such as waveform distortion or the like from the series of received data, and outputting waveform information based on the result of the estimation; and a correlator for correcting a reference and/or sample points on the basis of the recovered clock and the waveform information, obtaining a correlation value between the series of received data and the reference from a plurality of the sample points, and outputting demodulated data on the basis of the correlation value.

Demodulator, clock recovery circuit, demodulation method and clock recovery method

Distortion of a received signal due to intersymbol interference as well as to frequency offset is corrected. For this reason, a frequency offset correcting circuit corrects a received signal based on a frequency-offset estimated value. A first CIR estimating circuit estimates CIR estimated values at a first position according to a known training sequence in the corrected received signal. Also, a second estimating circuit updates the CIR estimated values with the LMS algorithm according to the corrected received signals as well as to the decision value outputted from the equalizer with the CIR estimated values at the first position as initial values and obtains CIR estimated values at a second position apart from the first position. A phase deviation detecting circuit computes phase deviations based on CIR estimated values at the first position as well as on CIR estimated values at the second position, and an averaging circuit averages the phase deviations, and outputs the averaged value to the frequency offset correcting circuit as a frequency-offset estimated value.

Receiver with a frequency offset correcting function

The prior art method of estimating a sequence by making use of a Viterbi algorithm is modified as follows: (1) A path at a certain past instant is modified to derive a modified path. (2) The path metric value of the modified path is calculated. (3) The path metric of a normal path and the path metric of the modified path are compared. If the path metric of the modified path is smaller, the path is modified. (4) A surviving path is selected from plural paths passing through the modified path.

Method of sequence estimation

A data transmission system, a receiver, and a recording medium in which a re-coder (,) generates pseudo transmission signals based on the virtual received data after a decoder (,) generates virtual received data based on virtual decision data from a virtual decision circuit (,), and a soft-decision circuit (,) outputs soft-decision data so as to decrease the number of different bits between the pseudo transmission signals and the received signals, and the received data are generated based on the soft-decision data.

Data transmission system, receiver, and recording medium

A digital data demodulating device that estimates the channel impulse response (CIR) based on a received signal, and performs a viterbi algorithm using the replica generated according to the estimated CIR, and the received signal. The digital data demodulating device of the present invention follows the time variation of the channel by sequentially estimating the CIR in the CIR estimating circuit. The replica generating circuit of the digital data demodulating device includes a device for storing the estimated CIR and replica for each block therein, for reading the estimated CIR at a specific timing and updating the replica. A digital data demodulating device which reduce circuit scale, operates in a high speed, and appropriately follows the time variation of the channel, even in a high bit transmission rate and in a high delay dispersion of the multipass wave contained in the received signal.

Digital data demodulating device for estimating channel impulse response

The presence or absence of a clock component is detected for an input signal. If the input signal does not comprise a clock component, the operation of a computing circuit is halted, thereby further improving the accuracy of phase estimation. A signal generating circuit produces a twiddle factor for DFT. A DFT circuit performs discrete Fourier transform on an input signal for a predetermined number of symbols based on the twiddle factor for DFT. A pattern detecting circuit examines the input signal for its pattern based on the output from the DFT circuit. An averaging filter turns on or off the operation of the subsequent averaging filter according to the detected pattern, and averages the outputs from the DFT circuit to remove a noise component.

Phase estimating circuit and demodulating circuit

A receiver capable of effecting frame synchronization control even at the time of initial acquisition and hand off in the presence of frequency selective fading. The receiver is provided in a demodulator part thereof with a quasi-coherent detector (140), a memory (144) for temporarily storing the output of the quasi-coherent detector, a write address counter (145) for the memory, an incoherent correlator (146) that determines correlation between a received data pattern and a known UW data pattern, a UW tentative detection circuit (147) that is supplied with the output of the address counter and the output of the incoherent correlator, an adaptive equalizer (148) that equalizes the received data stored in the memory by using the output of the UW tentative detection circuit, a UW detector (103) that effects UW position detection on the basis of the equalized data, and a frame synchronization control circuit (150) that effects frame synchronization control on the basis of the output of the UW tentative detection circuit and the output of the UW detector.

Adaptive equalizer and receiver

An adaptive equalizer comprising a computing unit which receives a known signal sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation which contains an interpolation of consecutive sets of tap coefficients between intermittent intervals.

Equalizer

'An adaptive equalizer comprising a computer unit which receives a known signals sequence to estimate transmission channel characteristics and effect compensatory control of tap coefficients by use of a first algorithm that has fast convergence property, and a tap coefficient computing unit for making compensation for relatively slow changes in a random data input after the compensation for the transmission channel characteristics, which either employs an algorithm that involves a relatively low computational complexity or intermittently executes computation.'

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Tokyo, Japan

Keishi Murakami