Hitachi, Ltd.

Keiko Kirino

Makoto Ono

Hisafumi Iwata

A method and system are provided for analyzing defects having the potential to become electrical failures, during the inspection of particles and/or pattern defects of a wafer used in the manufacture of electronic devices such as semiconductor integrated circuits. Defect map data is processed along with failure probability data. Next, defect-dependent failure probability calculations are made to obtain the failure probability of each defect in the defect map data. That data is then used to prepare failure-probability-added defect map data. Further, a selection process of defects to be reviewed is used to reorder and filter defects from the failure-probability-added defect map data, thus selecting one or more defects for review.

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Tokyo, Japan

Keiko Kirino