Kabushiki Kaisha Toshiba

Sony Corporation

Toshiba Memory Corporation

Fujitsu Corporation

Keiko Abe

Shinobu Fujita

Hiroki Noguchi

Kazutaka Ikegami

Kumiko Nomura

Shinichi Yasuda

Noboru Yanagita

Hiroaki Yoda

Naoharu Shimomura

Takumi Yoshida

Norifumi Zushi

Yuichi Ohsawa

Yoshiaki Saito

Yasushi Yamamoto

Shiho Nakamura

Hirofumi Morise

Tetsufumi Tanamoto

Takahiro Hirai

Masato Oda

Mototsugu Hamada

Susumu Takeda

Tadahiro Ohata

Nariyasu Hamahata

Koji Yanase

Tatsunori Kanai

Satoshi Shirotori

Katsuhiko Koui

Hitoshi Ikeda

Hideyuki Sugiyama

Tomoaki Inokuchi

Minoru Amano

Eiji Kitagawa

Junichi Ito

Masahiro Fujita

Yutaka Yamada

Satoshi Takagi

Masaya Tarui

Koichi Fujisaki

Chikayoshi Kamata

Chika Tanaka

Daisuke Saida

Yuuzo Kamiguchi

Satoshi Takaya

Hiroki Kotani

Nobuo Shirai

Christopher Grey

Masao Higuchi

A magnetic memory includes: first to third terminals; a conductive layer including first to fifth regions, the first region being electrically connected to the first terminal, the fifth region being electrically connected to the second terminal, and the third region being electrically connected to the third terminal; a first magnetoresistive element including a first magnetic layer, a second magnetic layer disposed between the second region and the first magnetic layer, and a first nonmagnetic layer disposed between the first and the second magnetic layer; a second magnetoresistive element including a third magnetic layer, a fourth magnetic layer disposed between the fourth region and the third magnetic layer, and a second nonmagnetic layer disposed between the third and the fourth magnetic layer; and a circuit flowing a write current between the first and the second terminal and between the second and the third terminal in a write operation.

Magnetic memory

A memory system has a nonvolatile memory to have a memory capacity equal to or less than a memory capacity of a volatile memory, and store at least a part of data stored in the volatile memory, a first controller to refresh data in the volatile memory, and a second controller to overwrite the nonvolatile memory with data read from the volatile memory in a first period between a second period to refresh data in the volatile memory and a third period to subsequently refresh data in the volatile memory.

Memory system having nonvolatile memory and volatile memory and processor system

A memory system has a non-volatile memory, an error corrector, an error information storage, and an access controller. The non-volatile memory comprising a plurality of memory cells. The error corrector to correct an error included in data read from the non-volatile memory. The error information storage, based on an error rate when a predetermined number or more of data is written in the non-volatile memory and read therefrom, to store first information on whether there is an error in the written data, on whether there is an error correctable by the error corrector in the written data, and on whether there is an error uncorrectable by the error corrector in the written data. The access controller, based on the first information, to control at least one of reading from or writing to the non-volatile memory.

Memory system

A magnetic memory includes: first to fourth wirings; first and second terminals; a first conductive layer including first to third regions, the second region being between the first region and the third region, the first region being electrically connected to the first terminal, and the third region being electrically connected to the second terminal; a first magnetoresistive element including a first and a second magnetic layer, and a first nonmagnetic layer disposed between the first and the magnetic layer; a first transistor including a third terminal electrically connected to the first magnetic layer, a fourth terminal electrically connected to the third wiring, and a first control terminal electrically connected to the first wiring; and a second transistor including a fifth terminal electrically connected to the first terminal, a sixth terminal electrically connected to the second wiring, and a second control terminal electrically connected to the first wiring.

Spin orbit torque (SOT) MRAM having a source line connected to a spin orbit conductive layer and arranged above a magnetoresistive element

A nonvolatile semiconductor memory includes a resistance-change element having first and second terminals, a transistor having third and fourth terminals and a control terminal, the third terminal being connected to the second terminal, and a first driver electrically connected to the control terminal, applying a first potential to the control terminal in a first write operation, and applying a second potential larger than the first potential to the control terminal in a second write operation.

Nonvolatile resistance changing semiconductor memory using first and second writing operations

According to one embodiment, a processor includes a core controlling processing data, a cache data area storing the processing data as cache data in a nonvolatile manner, a first tag area storing a tag data of the cache data in a volatile manner, a second tag area storing the tag data in a nonvolatile manner, a tag controller controlling the tag data. The tag controller determines whether the processing data is stored in the cache data area by acquiring the tag data from one of the first and second tag areas.

Processor

According to one embodiment, a system includes: a device including a memory cell array, the device configured to execute first read operation of a first read method and second read operation of a second read method on the memory cell array; a processor configured to receive a first data from the device, the first data from a selected region in the memory cell array by the first read operation, configured to execute first calculation processing using the first data during the second read operation to the selected region, and configured to acquire a result of the first calculation processing by a first signal based on a comparison result of the first data and a second data, the first signal indicating that the first data is valid, and the second data from the selected region by the second read operation.

Computer system and memory device

A memory control circuit has an error determination circuitry to determine whether an error-bit number is larger than a predetermined threshold value set based on a maximum number of error bits correctable by the error correction circuitry, when it is detected by the error detector that an error is contained in data read for verification of data written to the first memory or in data read from the first memory, and an access controller to control access to a second memory having an access priority lower than the first memory when it is determined that the error-bit number is larger than the threshold value, and to control access to the first memory without accessing the second memory when it is determined that the error-bit number is equal to or less than the threshold value.

Memory control circuit, cache memory and memory control method

A memory control circuit has a request determination circuitry to determine whether a period without read-out request and write request to an i-th (i being an integer of 1 or more and of n or less, n being an integer of 2 or more) level cache memory among first to n-th level cache memories continues for a first period of time or longer, the i-th level cache memory comprising a first nonvolatile memory, and a power-supply controller to control a power cut-off timing to the i-th level cache memory based on a determination of the request determination circuitry.

Memory control circuit and processor

A storage device according to an embodiment includes: first and second magnetic elements each including: a reference layer connected to a third terminal; a first magnetic layer including first through third magnetic regions; a nonmagnetic layer; a second magnetic layer connected to a first terminal and the first magnetic region; and a third magnetic layer connected to a second terminal and the third magnetic region; a first inverter including a p-channel first transistor, an n-channel second transistor, a first input terminal connected to the second terminal of the second magnetic element, and a first output terminal connected to the first terminal of the first magnetic element; and a second inverter including a p-channel third transistor, an n-channel fourth transistor, a second input terminal connected to the second terminal of the first magnetic element, and a second output terminal connected to the first terminal of the second magnetic element.

Storage device including magnetic elements

According to an embodiment, a cache device includes a cache memory, an access controller, and a power controller. The cache memory includes a plurality of memory areas associated with a plurality of ways, respectively. The access controller controls access to the memory areas. The power controller controls power supplied to each of the memory areas individually such that power supplied to a memory area that has not been accessed for a predetermined time is standby power that is lower than operating power that enables the memory area to operate. The power controller controls power supplied to a memory area such that standby power for a memory area that is highly likely to be accessed has a value closer to the operating power than a value of standby power for a memory area that is less likely to be accessed.

Cache device, cache system and control method

According to one embodiment, a magnetic random access memory includes a write circuit to write complementary data to first and second magnetoresistive elements, and a read circuit to read the complementary data from the first and second magnetoresistive elements. The control circuit is configured to change the first and second bit lines to a floating state after setting the first and second bit lines to a first potential, and change a potential of the first bit line in the floating state to a first value in accordance with a resistance value of the first magnetoresistive element and a potential of the second bit line in the floating state to a second value in accordance with a resistance value of the second magnetoresistive element by setting the common source line to a second potential higher than the first potential.

Magnetic random access memory

According to one embodiment, a semiconductor device includes a processor chip, and a memory chip stacked on the processor chip with bumps and including a memory cell unit and a memory logic unit. The bumps are arranged on the memory logic unit. An address and data are transferred between the processor chip and the memory chip by use of shared bumps of the bumps.

Semiconductor device having stacked chips

According to one embodiment, a processor system includes a variable capacity memory. The memory includes a memory cell array including basic units, each of the basic units including one cell transistor and one variable resistance element, a mode selector switching between first and second modes, a read/write of one bit executed in 2basic units (n is an integer) among the basic units in the first mode, the read/write of the one bit executed in 2basic units (m is an integer, m&#x2260;n) among the basic units in the second mode, and a control circuit which controls the switching between the first and second modes.

Processor system having variable capacity memory

Growing community of inventors

Yokohama, Japan

Keiko Abe