Hitachi, Ltd.

Keiki Watanabe

Hideki Koba

Kouji Fukuda

Satoshi Ueno

Takashi Muto

Takashi Harada

Fumio Yuki

An adaptive equalizer includes: a speculative equalization circuit which operates a plurality of first tap coefficients with respect to input data and selects operation data corresponding to the input data from a plurality of operation data obtained by the operation; and an adaptive equalization circuit which generates the plurality of first tap coefficients, on the basis of the input data. The adaptive equalization circuit includes: an operation circuit which selects one of a plurality of second tap coefficients corresponding to the plurality of first tap coefficients and operates the selected second tap coefficient with respect to the input data; and a tap coefficient generation circuit which generates the plurality of first tap coefficients, on the basis of operation data obtained by the operation of the operation circuit, when the second tap coefficient selected at the time of the operation in the operation circuit corresponds to the first tap coefficient used for the operation of the operation data selected in the speculative equalization circuit.

Adaptive equalizer

A semiconductor device capable of achieving high speed performance in addition to correction of differential offset and a communication device provided with the semiconductor device are provided. For example, there are provided: a variable gain type differential amplifier circuit VGAwhich receives a gain setting signal ASET, which amplifies differential input signals INP and INN by a gain indicated by the gain setting signal, and which outputs differential output signals OUTP' and OTUN&#x2032;; and an offset correcting circuit unit OFCBKwhich cancels an offset voltage (VOF and VOFO) generated in the VGA. Here, the OFCBKcancels an output offset voltage VOFO (which results in an input offset voltage VOF) by receiving the ASET, generating a correction voltage changed in accordance with the gain, and adding the correction voltage to the OUTP&#x2032; and OUTN&#x2032;.

Semiconductor device and communication device

Power consumption is increased in an interface circuit having a signal processing function for waveform shaping due to influence of a circuit added for waveform shaping. Also, since a plurality of boards are connected to a backplane in a system, they are not exchanged in accordance with distances while there are boards being far or near are mixed, but a common board is used. Thus, it is necessary to prepare a configuration of an interface circuit meeting the longest transfer distance. An interface circuit disabling a part of or all of operations of a waveform shaping circuit is provided. Accordingly, in accordance with transfer distances, switching of operation ranges of waveform shaping circuit inside the interface circuit is possible, and operation ranges of the waveform shaping circuit can be limited, and power consumption of the interface circuit, an LSI including the interface circuit, and a server device can be reduced.

Interface circuit, LSI, server device, and method of training the interface circuit

A semiconductor integrated circuit device includes a transmitting circuit capable of converting first parallel signals to a first serial signal, a receiving circuit capable of converting a second serial signal to second parallel signals, a test signal generating circuit, and an operation judging circuit, all of which are formed on a single semiconductor chip. The test signal generating circuit and the operation judging circuit are formed so as to operate in accordance with a clock having a frequency corresponding to a transfer rate of the first or second parallel signals.

Growing community of inventors

Tachikawa, Japan

Keiki Watanabe