Sumitomo Electric Industries, Limited

Nag System Co., Ltd.

Keiji Wada

Toru Hiyoshi

Takeyoshi Masuda

Taro Nishiguchi

Shin Harada

Hironori Itoh

Kosuke Uchida

Misako Honaga

Tsutomu Hori

Yu Saitoh

Hideto Tamaso

Mitsuhiko Sakai

Hiromu Shiomi

Tomihito Miyazaki

Satomi Itoh

Kyoko Okita

Makoto Sasaki

Mitsuru Shimazu

Masaki Furumai

Takaya Miyase

Kenji Kanbara

Hidemasa Nagamine

Taku Horii

Hiroyuki Kitabayashi

Hideki Hayashi

Takashi Tsuno

Yasuo Namikawa

Shunsuke Yamada

Ryosuke Kubota

Hideyuki Doi

Jun Genba

Shinji Matsukawa

Takemi Terao

Masato Tsumori

Takahiro Asada

A sealing method that uses an electrostatic energy storage welding machine which includes an energy storage section including a plurality of energy storage parts is provided. A method of sealing a liquid inlet port of a power storage device includes burring in advance a through-hole of the liquid sealing port to raise a hole edge of the through-hole into a form of a projection, wherein the liquid sealing port of the power storage device to be sealed with electrolyte contained therein corresponds to an object to be welded; placing a spherical body that is a lid body on the projection; and performing resistance welding between the projection and the spherical body to seal the liquid inlet port.

Sealing method for liquid inlet port of power storage device

A first main surface is a (000-1) plane or a plane inclined by an angle of less than or equal to 8° relative to the (000-1) plane. A substrate placement surface has an area of more than or equal to 697 cmand less than or equal to 1161 cm. When an X axis indicates a first value and a Y axis indicates a second value, the first value and the second value fall within a hexagonal region surrounded by first coordinates, second coordinates, third coordinates, fourth coordinates, fifth coordinates and sixth coordinates in XY plane coordinates, where the first coordinates are (0.038, 0.0019), the second coordinates are (0.069, 0.0028), the third coordinates are (0.177, 0.0032), the fourth coordinates are (0.038, 0.0573), the fifth coordinates are (0.069, 0.0849), and the sixth coordinates are (0.177, 0.0964).

Method for manufacturing silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device

A first main surface is a (000-1) plane or a plane inclined by an angle of less than or equal to 8&#xb0; relative to the (000-1) plane. A reaction chamber has a cross-sectional area of more than or equal to 132 cmand less than or equal to 220 cmin a plane perpendicular to a direction of movement of a mixed gas. When an X axis indicates a first value and a Y axis indicates a second value, the first value and the second value fall within a hexagonal region surrounded by first coordinates, second coordinates, third coordinates, fourth coordinates, fifth coordinates and sixth coordinates in XY plane coordinates, where the first coordinates are (0.038, 0.0019), the second coordinates are (0.069, 0.0028), the third coordinates are (0.177, 0.0032), the fourth coordinates are (0.038, 0.0573), the fifth coordinates are (0.069, 0.0849), and the sixth coordinates are (0.177, 0.0964).

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. In a direction parallel to a central region, a ratio of a standard deviation of a carrier concentration of the silicon carbide layer to an average value of the carrier concentration of the silicon carbide layer is less than 5%. The average value of the carrier concentration is more than or equal to 1&#xd7;10cmand less than or equal to 5&#xd7;10cm. In the direction parallel to the central region, a ratio of a standard deviation of a thickness of the silicon carbide layer to an average value of the thickness of the silicon carbide layer is less than 5%. The central region has an arithmetic mean roughness (Sa) of less than or equal to 1 nm. The central region has a haze of less than or equal to 50.

Silicon carbide epitaxial substrate and method for manufacturing silicon carbide semiconductor device

A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. An average value of carrier concentration in the silicon carbide layer is not less than 1&#xd7;10cmand not more than 5&#xd7;10cm. In-plane uniformity of the carrier concentration is not more than 2%. The second main surface has: a grooveextending in one direction along the second main surface, a width of the groove in the one direction being twice or more as large as a width thereof in a direction perpendicular to the one direction, and a maximum depth of the groove from the second main surface being not more than 10 nm; and a carrot defect. A value obtained by dividing a number of the carrot defects by a number of the grooves is not more than 1/500.

Silicon carbide epitaxial substrate having grooves extending along main surface and method of manufacturing silicon carbide semiconductor device

Assuming that one or more defects satisfying relations of Formula 1 and Formula 2 are first defects, and one or more defects satisfying relations of Formula 3 and Formula 2 are second defects, where an off angle is &#x3b8;&#xb0;, the thickness of a silicon carbide layer in a direction perpendicular to a second main surface is W &#x3bc;m, the width of each of the one or more defects in a direction obtained by projecting a direction parallel to an off direction onto the second main surface is L &#x3bc;m, and the width of each of the one or more defects in a direction perpendicular to the off direction and parallel to the second main surface is Y &#x3bc;m, a value obtained by dividing the number of the second defects by the sum of the number of the first defects and the number of the second defects is greater than 0.5.

It is assumed that a defect satisfying relations of Formula 1 and Formula 2 is a first defect, where an off angle is &#x3b8;. It is assumed that a defect having an elongated shape when viewed in a direction perpendicular to the second main surface, and satisfying relations of Formula 3 and Formula 4 is a second defect. A value obtained by dividing the number of the second defect by the sum of the number of the first defect and the number of the second defect is greater than 0.5.

A semiconductor device has a semiconductor layer and a substrate. The semiconductor layer constitutes at least a part of a current path, and is made of silicon carbide. The substrate has a first surface supporting the semiconductor layer, and a second surface opposite to the first surface. Further, the substrate is made of silicon carbide having a 4H type single-crystal structure. Further, the substrate has a physical property in which a ratio of a peak strength in a wavelength of around 500 nm to a peak strength in a wavelength of around 390 nm is 0.1 or smaller in photoluminescence measurement. In this way, the semiconductor device is obtained to have a low on-resistance.

Semiconductor device and method for manufacturing same

In forming of a silicon carbide layer, when an X axis indicates a first value representing, in percentage, a value obtained by dividing a flow rate of silane by a flow rate of hydrogen and a Y axis indicates a second value representing a flow rate of ammonia in sccm, the first value and the second value fall within a quadrangular region surrounded by first coordinates, second coordinates, third coordinates, and fourth coordinates in XY plane coordinates. The first coordinates are (0.05, 6.5&#xd7;10). The second coordinates are (0.05, 4.5&#xd7;10). The third coordinates are (0.22, 1.2&#xd7;10). The fourth coordinates are (0.22, 1.3&#xd7;10). After the forming of the silicon carbide layer, an average value of carrier concentration of the silicon carbide layer is more than or equal to 1&#xd7;10cmand less than or equal to 2&#xd7;10cm.

Method for manufacturing silicon carbide epitaxial substrate, method for manufacturing silicon carbide semiconductor device, and apparatus for manufacturing silicon carbide epitaxial substrate

A silicon carbide semiconductor device includes a silicon carbide substrate and a gate insulating film. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The gate insulating film is provided on the first main surface. The silicon carbide substrate includes a first body region having p type, a second body region having p type, and a JFET region provided between the first body region and the second body region and having n type. The JFET region has both a first impurity capable of providing the p type and a second impurity capable of providing the n type. A concentration of the second impurity is higher than a concentration of the first impurity. The silicon carbide semiconductor device capable of suppressing dielectric breakdown of the gate insulating film is provided.

Silicon carbide semiconductor device

A silicon carbide epitaxial substrate has a silicon carbide single-crystal substrate and a silicon carbide layer. An average value of carrier concentration in the silicon carbide layer is not less than 1&#xd7;10cmand not more than 5&#xd7;10 cm. In-plane uniformity of the carrier concentration is not more than 2%. The second main surface has: a grooveextending in one direction along the second main surface, a width of the groove in the one direction being twice or more as large as a width thereof in a direction perpendicular to the one direction, and a maximum depth of the groove from the second main surface being not more than 10 nm; and a carrot defect. A value obtained by dividing a number of the carrot defects by a number of the grooves is not more than 1/500.

Silicon carbide epitaxial substrate having a silicon carbide layer and method of manufacturing silicon carbide semiconductor device

A silicon carbide epitaxial substrate includes a silicon carbide single crystal substrate and a silicon carbide layer. The silicon carbide single crystal substrate has a first main surface. The silicon carbide layer is on the first main surface. The silicon carbide layer includes a second main surface opposite to a surface thereof in contact with the silicon carbide single crystal substrate. The second main surface has a maximum diameter of more than or equal to 100 mm. The second main surface includes an outer peripheral region which is within 3 mm from an outer edge of the second main surface, and a central region surrounded by the outer peripheral region. The central region has a haze of less than or equal to 75 ppm.

A method for manufacturing a silicon carbide epitaxial substrate includes epitaxially growing a first layer on a silicon carbide single crystal substrate, and forming a second layer at an outermost surface of the first layer. The second layer has a chemical composition or density different from that of the first layer. A ratio of a thickness of the second layer to a thickness of the first layer is more than 0% and less than or equal to 10%.

Method for manufacturing silicon carbide epitaxial substrate, silicon carbide epitaxial substrate, method for manufacturing silicon carbide semiconductor device, and silicon carbide semiconductor device

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Osaka, Japan

Keiji Wada