Sumitomo Electric Industries, Limited

Shell Oil Comapny

Other

Tokyo Metropolitan Institute of Medical Science

Kddi Corporation

Kdd Corporation

Fujitsu Corporation

Panasonic Intellectual Property Management Co., Ltd.

Ebara Corporation

Panasonic Communications Co., Ltd.

Hitachi Appliances, Inc

Showa Shell Sekiyu K.k.

Kddi Submarine Cable Systems Inc.

Keiji Tanaka

Naoki Itabashi

Yoshiyuki Sugimoto

Hiroshi Uemura

Taichi Misawa

Noboru Edagawa

Taizo Tatsumi

Yasushi Kawamura

Akihiro Moto

Masatoshi Suzuki

Kazuya Watanabe

Katsumi Uesaka

Takehiro Tsuritani

Noriaki Shinoda

Yasushi Saeki

Seiji Kumagai

Hikaru Tsuchiya

Shu Yamamoto

Makoto Ito

Sosaku Sawada

Tadashi Araki

Akihiro Kamemura

Seigo Furudate

Tetsuo Nimura

Kenji Kutsuki

Ai Kaiho

Kazushige Ohmura

Kenji Tojo

Shinichi Watanabe

Hidenori Taga

Satoshi Kikuchi

Toshiharu Nakazawa

Shinya Nakamura

Yutaka Mori

Koji Arimura

Naoya Kono

Akira Takenaka

Takeo Yamamoto

Chie Fukuda

Takashi Maehata

Hiroyuki Mikami

Tetsuro Sugiura

Phillip J Edwards

Yasuyuki Yamauchi

Kazuhiro Yamaji

Takumi Matsumoto

Noriyuki Hirakata

Masashi Miyake

Tomoyuki Yamazaki

Masaru Ohtahara

Takahiro Ozaki

Tomio Yoshikawa

Hideo Morita

Baiying Huang

Akeshi Takahashi

Kenichiro Uchida

Morihiro Seki

Kazuhiro Miyajima

Kazuo Sakurai

Kiyoshi Terai

Koichi Kido

Yasuro Ohishi

Tomoko Miura

Kiyoshi Fukatsu

Ryuichi Masumori

Tomoko Ikagawa

Motoshi Hayashi

Toshio Nagatsuka

Kouichi Nakazawa

Hiroki Yano

Hiroyuki Imamura

Yoshihisa Yatsuzuka

Tadashi Sato

Shinya Okuda

Hideyuki Kumakura

Kouji Saitou

Hirofumi Kuwabara

Yukiko Yoshida

Tomoyasu Wada

Arisa Murakami

Kazuo Yakuwa

Takashi Ishikawa

Takashi Ooyama

Taizou Tatsumi

Toshiki Satou

Toshihiro Asakura

Shigeyuki Sugimori

An amplifier circuit includes a first cascode transistor and a second cascade transistor, the first cascade transistor being electrically connected between a first transistor and a first load circuit, the second cascode transistor being electrically connected between a second transistor and a second load circuit. The amplifier circuit includes a first shunt transistor and a second shunt transistor, the first shunt transistor being electrically connected between the first transistor and a first emitter-follower circuit, the second shunt transistor being electrically connected between the second transistor and a second emitter-follower circuit. A differential current signal includes a first differential current and a second differential current, the first differential current flowing through the first cascode transistor and the second cascode transistor, and a second differential current flowing through the first shunt transistor and the second shunt transistor.

Amplifier circuit

An optical module includes: a housing having a first face and a second face parallel to the first face; a first block fixed to the first face of the housing by a first adhesive; an integrated circuit (IC) fixed to the first block by a second adhesive having a thickness larger than a thickness of the first adhesive; a thermoelectric cooler (TEC) fixed to the second face of the housing; an optical circuit element fixed to the TEC; and an interconnection board mounted on the IC and the optical circuit element, the interconnection board being configured to electrically couple the IC to the optical circuit element. The first block is sandwiched between the housing and the IC. The TEC is sandwiched between the housing and the optical circuit element.

Optical module and manufacturing method of optical module for optical communication

A reception circuit includes an input terminal configured to receive an input current; a voltage signal circuit being configured to convert a current signal into a voltage signal; a reference voltage circuit configured to generate a reference voltage in accordance with a first feedback current; a differential amplifier circuit configured to generate a differential signal in accordance with a voltage difference between the voltage signal and the reference voltage; and an offset control circuit configured to generate the first feedback current and a second feedback current, adjust the first feedback current when the voltage signal has an average voltage value greater than the reference voltage, and subtract the second feedback current from the input current such that the offset of the differential signal falls within the tolerance when the voltage signal has an average voltage value smaller than the reference voltage.

Reception circuit for optical communication

A package for an optical module includes a substrate that includes a first wiring layer, a second wiring layer, and a third wiring layer. The package includes a first insulating layer between the first wiring layer and the second wiring layer, the first insulating layer including first vias. The package includes a second insulating layer between the second wiring layer and the third wiring layer, the second insulating layer including second vias and third vias. Each first vias is provided between a corresponding second via and a corresponding third via. The first vias are arranged at a first interval along a first direction. The second vias are arranged at a second interval along the first direction. Each second vias is disposed at an offset by half of the second interval from the corresponding third via.

Optical module assembly, optical module, package for optical module and flexible printed board

An output circuit includes: an inductor, an amplifier circuit that outputs an output signal via the inductor, an output terminal that outputs the output signal to an outside, a voltage divider circuit including a series circuit constituted by a first capacitive element and a second capacitive element connected in series to the first capacitive element, the series circuit generating a first voltage-divided signal by dividing a voltage of the output signal, a first band-adjusting element having a resistance component for generating a first band-adjusted signal by adjusting frequency characteristics of the first voltage-divided signal, and a first peak detection circuit that detects a peak voltage of the first band-adjusted signal and output a first peak voltage in accordance with the detected peak voltage.

Output circuit with peak voltage detection

A package for an optical module includes a substrate provided through a side wall in a first direction. The substrate includes a first wiring layer including a first signal terminal, a second signal terminal, and a first ground terminal. The package includes a second wiring layer disposed under the first wiring layer. The second wiring layer includes a first ground pattern and a first insulating layer disposed between the first wiring layer and the second wiring layer, and includes a groove extending along the first direction, the groove being filled with a metal. The groove is provided within the first ground terminal, in a plan view, and the first insulating layer is free of the groove. The first ground terminal is electrically coupled to the first ground pattern through the metal of the groove.

According to one embodiment, an optical module includes: a lid having a first face and a second face, the lid including a bump, a wiring, and a through via; an optical circuit element; a first integrated circuit (IC); a first block bonded to the first IC by a first adhesive; a temperature control element bonded to the optical circuit element; and a housing having an opening and a third face provided inside the opening, the housing being configured to house the first IC, the optical circuit element, the first block, and the temperature control element, the third face being bonded to the first block and the temperature control element by a second adhesive, the housing being hermetically sealed with the lid.

A variable gain amplifier circuit includes first and second input terminals, first and second output terminals, first and second transistors respectively having bases electrically connected to the first and second input terminals and having collectors electrically connected to the first and second output terminals, and a degeneration circuit connected between emitters of the first and second transistors. The degeneration circuit has first and second MOS transistors each having two current terminals connected in series between the emitters of the first and second transistors, series resistor circuits, first and second current sources, two resistive elements connected between the first and second current sources and gates of the first and second MOS transistors, and two resistive elements connected between the first and second current sources and two nodes of the series resistor circuits.

Variable gain amplifier circuit and semiconductor integrated circuit

A receiver circuit includes an input terminal for receiving an input current signal, a transimpedance amplifier having an input node, the transimpedance amplifier converting a current signal input to the input node into a voltage signal, an inductor having a first terminal and a second terminal, and a bypass circuit. The first terminal is coupled to the input terminal and the second terminal is coupled to the input node. The bypass circuit includes a bias circuit supplying a bias voltage, a first variable resistor coupled between the first terminal and the bias circuit, a second variable resistor coupled between the second terminal and the bias circuit, and an impedance adjustment circuit including a resistor and a capacitor connected in parallel to the resistor, the impedance adjustment circuit connected in series to at least one of the first variable resistor and the second variable resistor.

Receiver circuit for optical communication

An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a common node, a second diode circuit connected between the second output terminal and the common node, an intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at the common node, an intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, and a clamp circuit configured to electrically connect the common node to a ground line in accordance with the intermediate voltage.

Electrostatic protection circuit and semiconductor integrated circuit

A driving circuit includes first and second input signal terminals, first and second output signal terminals, constant current sources, first and second transistors having control terminals connected to the first and second input signal terminals, third and fourth transistors each having a control terminal to which a first bias voltage is applied, first and second inductors each having a first inductance, and third and fourth inductors each having a second inductance larger than the first inductance. The driving circuit further includes fifth and sixth transistors each having a control terminal to which a second bias voltage is applied, outflow terminals connected to inflow terminals of the third and fourth transistors via the first and second inductors, and inflow terminals connected to the first and second output signal terminals via the third and fourth inductors.

Driving circuit and semiconductor integrated circuit for use in an optical communication device

An electrostatic protection circuit includes first and second output terminals, a first diode circuit connected between the first output terminal and a first node, a second diode circuit connected between the second output terminal and the first node, a first intermediate voltage circuit that is connected between the first output terminal and the second output terminal and that is configured to generate, at a second node different from the first node, a first intermediate voltage having an intermediate voltage value between a voltage value of the first output terminal and a voltage value of the second output terminal, a detection circuit configured to generate a trigger signal in accordance with the first intermediate voltage, and a switch circuit configured to electrically connect the first node to a ground line in accordance with the trigger signal.

A printed board includes a first wiring layer including a first terminal, a second wiring layer including a second terminal facing to the first terminal, a dielectric layer interposed between the first wiring layer and the second wiring layer and having an end face, and a plurality of through-hole vias configured to electrically connect the first terminal and the second terminal. The plurality of through-hole vias includes a first through-hole via which is closest to an end-face edge of the first terminal, and a second through-hole via which is closest to an inner edge of the second terminal. The end-face edge being closer to the end face than the inner edge. A distance between the first through-hole via and the end-face edge is equal to or smaller than one eighth of a signal wavelength of a high speed signal transmitted through the first terminal.

Printed board and printed board assembly

A transimpedance amplifier includes a feedback circuit that generates a bypass current in accordance with a charging voltage of a capacitor based on a difference between a voltage signal and a reference voltage signal, a differential amplifier circuit that generates a differential signal in accordance with the difference between the voltage signal and the reference voltage signal, and a detector circuit that resets the charging voltage of the capacitor in response to a detection of end of a burst optical signal. The feedback circuit detects start of the burst optical signal based on the charging voltage, maintains a time constant at a first time constant for a predetermined period from the detection of the start of the burst optical signal, and, upon an elapse of the predetermined period, switches the time constant from the first time constant to a second time constant larger than the first time constant.

Transimpedance amplifier for receiving burst optical signal

An optical receiver disclosed includes a bias terminal, an input terminal, a photodiode, an amplifier circuit, a first resistor, a bypass circuit, a filter circuit, and a control circuit. The photodiode receives a bias from the filter circuit through the bias terminal, and outputs a current signal to the amplifier circuit through the input terminal. The amplifier circuit converts an input current to an output voltage. The bypass circuit electrically connected to the input terminal decreases a first input impedance viewed from the input terminal, when activated, and increases the first input impedance, when deactivated. The filter circuit increases a second input impedance viewed from the bias terminal, when a dumping function thereof is activated, and decreases the second input impedance, when the dumping function is deactivated. The control circuit activates the dumping function and the bypass circuit, when the output voltage is larger than a certain voltage.

Optical receiver and transimpedance amplifier circuit

Growing community of inventors

Yokohama, Japan

Keiji Tanaka