Ando Electric Company

Keiji Negi

Sort operations of an input signal are performed by providing a first sort part 6 comprising one shift circuit 8 and (l&#x2212;1) sort circuitsto, and a second sort part 7 comprising one delay circuit 10, (m&#x2212;1) sort circuitstoand m shift circuitstoin a pattern synchronous circuit 100.

Pattern synchronous circuit

A pull-in circuit of the present invention which can shorten the time of the pull-in operation. The pull-in circuit comprises: a pseudo-random pattern operating circuit for operating an operated pseudo-random pattern on the basis of consecutive bits of the parallel receiving data; a comparison circuit for comparing the operated pseudo-random pattern with a receiving pattern of the receiving data corresponding to the operated pseudo-random pattern; a one-shot circuit for passing a first pulse outputted from the comparison circuit when the operated pseudo-random pattern is coincident with the receiving pattern; a parallel pseudo-random pattern generation circuit for generating the reference parallel pseudo-random pattern when the first pulse passes through the one-shot circuit; a delay circuit for delaying the receiving data; and a bit error detection circuit for detecting a bit error, which compares the receiving data outputted from the delay circuit with the reference parallel pseudo-random pattern.

Pull-in circuit for pseudo-random pattern

A light modulation device includes a lithium niobate light modulator, an amplifier, and a bias control circuit. The lithium niobate light modulator modulates light from a light source in accordance with an input electrical signal, and outputs the modulated light. The lithium niobate light modulator includes a terminal for terminating the electrical signal. The amplifier amplifies the electrical signal to a level where it can drive the lithium niobate light modulator, and outputs the amplified signal to the lithium niobate light modulator. The amplifier includes an amplifying element at an output stage. A bias voltage of the amplifying element is set by externally supplied DC voltages. The bias control circuit supplies the DC voltages to the amplifying element, and a DC operating voltage to the terminating terminal of the lithium niobate light modulator to set a modulation operating point of the lithium niobate light modulator.

Light modulation device

A bit error measurement circuit is designed to measure a number of bit errors by comparing receiving data with a reference Pseudo-Noise pattern. Herein, a certain PN pattern is used as the receiving data in order to perform testing in performance of communications and transmission by evaluating the receiving data. There are provided multiple kinds of PN patterns each having a specific PN-stage number. The bit error measurement circuit is capable of automatically detecting a PN-stage number with respect to the receiving data. One method to do so is to perform comparison between the receiving data and an arbitrary pattern at timings which are periodically set to correspond to all PN-stage numbers each having a probability to be related to the receiving data, wherein the arbitrary pattern is extracted from the receiving data. Thus, the PN-stage number is automatically detected in response to the timing at which the receiving data coincide with the arbitrary pattern. Another method is to extract consecutive-0s patterns and consecutive-1s patterns from the receiving data and to perform comparison between a count value, corresponding to a number of bits of a longest consecutive-0s pattern, and a count value corresponding to a number of bits of a longest consecutive-1s pattern. So, a PN-stage number and a logic are detected based on result of the comparison between the count values. Thus, a reference PN pattern is generated based on the PN-stage number and the logic.

Bit error measurement circuit

The present invention relates to pseudo-random pattern generating circuit for outputting pseudo-random patterns of a plurality of pseudo-random stages, characterized in comprising: a plurality of latch circuits for conducting delayed output of data input in synchrony with a clock input; a multiple input exclusive OR arithmetic circuit, an output of which is inputted into the aforementioned latch circuits; and a select circuit for selecting an output of the latch circuit and inputting this output as input data to the exclusive OR arithmetic circuit; wherein the select circuit switches an output to the exclusive OR arithmetic circuit according to an inputted select signal. In addition, it is also possible for the pseudo-random pattern generating circuit to further comprise a decoding circuit for converting an inputted pseudo-random selection signal to a select signal, and outputting this select signal.

Pseudo-random pattern generating circuit

A counter circuit having a load function which is able to speedily yet stably perform counting operations no matter what kind of value has been loaded. The counter circuit having a load function performs counting operations in synchronization with an input clock signal and is able to count from an arbitrary value upon receiving a count initiation value in synchronization with a load signal. The principal composing elements are: at least three counter circuits 1-1.about.1-N, each of which corresponds to a numerical digit; at least one load value monitor circuit 2-i (wherein i is an integer between 3 and N), which detects whether or not load values of the counter circuits 1 corresponding to lower digits are full count values upon input of the count initiation value in synchronization with the load signal, and delays the output of the load signal by one clock period if a full-count value has been detected; and at least one OR circuit 3-i, which receives an output from load value monitor circuit 2-i and a carry output from counter circuit 1-(i-1), then outputs their logical sum to an ET terminal of counter circuit 1-i.

Counter circuit having load function

A testing device is provided to test performance of transmission systems such as communication devices and transmission lines by transmitting and receiving specific patterns called pseudo-random patterns (i.e., PN patterns). A receiver unit of the testing device provides a synchronization detecting circuit. The synchronization detecting circuit comprises a pseudo-random-pattern creating circuit, a first coincidence detecting block, a second coincidence detecting block and an OR circuit. The first coincidence detecting block detects coincidence between a receiving-data input, a first detected-pattern input and a pseudo-random pattern created by the pseudo-random-pattern creating circuit so as to produce a first coincidence detecting signal. The second coincidence detecting block detects coincidence between the receiving-data input, a second detected-pattern input and the pseudo-random pattern so as to produce a second coincidence detecting signal. The first and second coincidence detecting signals are applied to the OR circuit, by which a synchronous detection signal is produced. Thus, synchronization between the receiving-data input and pseudo-random pattern is detected by the synchronous detection signal. Incidentally, each of the first and second detected-pattern inputs receives the pseudo-random pattern transmitted thereto through the transmission system; and the second detected-pattern input is delayed behind the first detected-pattern input by `m` bits (where `m` is an integer which is determined in advance).

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Tokyo, Japan

Keiji Negi