Waseda University

Sony Corporation

Hitachi, Ltd.

Denso Corporation

Renesas Electronics Corporation

Olympus Corporation

Hitachi Rail Sts S.p.a.

Keiji Kimura

Hironori Kasahara

Yoichiro Sako

Masamichi Asukai

Taiji Ito

Hidehiko Sekizawa

Masaaki Tsuruta

Akinobu Sugino

Nozomu Ozaki

Yonetaro Totsuka

Hiroaki Shikano

Dan Umeda

Hiroki Mikami

Kan Ebisawa

Masaki Ito

Tsuyoshi Minakawa

Jun Shirako

Tatsuya Kamei

Toshihiro Hattori

Noriyuki Suzuki

Michi Kariatsumari

Hirofumi Nakano

Yoshihiro Kawano

Masayuki Ito

Akihiro Hayashi

Iwao Kanamori

Hiroshi Mori

Tsuyoshi Miura

Masayoshi Mase

Kenichi Mineda

Ryota Uematsu

Takashi Todaka

Yoshihiro Yatou

Mitsumori Hayashida

Miki Yonehara

Takanori Maruyama

Tomohiro Tagawa

Yasutaka Wada

Tatsuhiro Satou

Claudio Giorgianni

Megumi Yamaguchi

Masahito Kokubo

Kazushi Nobuta

Mitsuhiro Tani

Yohei Kanehagi

Takumi Nito

Mitsuo Sawada

A timetable creation apparatusfor correcting a target timetable being a train timetable to be used to control a group of trains by using a predicted passenger demand to thereby create a new target timetable, includes: an objective function generation unitthat generates an objective function for an operation headway between trains included in the group of trains by using the predicted passenger demand; a constraint condition generation unitthat derives constraint conditions which an arrival time and a departure time of each of the trains at each of stations should satisfy for operation of the group of trains; and a candidate timetable creation unitthat creates a candidate timetable as an update candidate for a target timetable by using an arrival time and a departure time of each of the trains at each of the stations derived by optimizing the objective function under the constraint conditions.

Timetable creation apparatus, timetable creation method, and automatic vehicle control system

The present invention makes it possible to supply transportation capacity suitable for movement demand in numerous circumstances. A timetable modification device for changing a timetable representing a train control target, in accordance with a movement demand prediction result indicating, for each time period, the number and destination of passengers at each station at which the train stops, the timetable modification device having a violation position extraction program Pfor calculating the degree of congestion of a train on the basis of predicted demand information representing a movement demand prediction result and extracting a violation position at which the degree of congestion is outside a predetermined allowed range, and a timetable correction program Pfor changing a timetable so as to include a change in the destination of the train so that the degree of congestion of the violation position is within the allowed range or so that the degree of congestion of the violation position approaches the allowed range.

Timetable modification device and automatic train control system

When input information including starting point information and destination information are input, this transport navigation system searches for a route for traveling from the starting point to the destination by a train of a transportation means on the basis of the input information, and outputs travel route information about the travel route obtained. The transport navigation system includes: a storage unit which stores the input information, an actual timetable including actual operation of the train, and a software program; and a CPU which executes the software program with reference to the input information and the actual timetable. The CPU calculates, on the basis of the actual timetable and the input information, the travel route from the starting point to the destination and a statistical amount about a travel time according to the travel route, and generate travel route information on the basis of the travel route and the statistical amount.

Transport navigation system and transport navigation method

There is provided a parallel program generating method capable of generating a static scheduling enabled parallel program without undermining the possibility of extracting parallelism. The parallel program generating method executed by the parallelization compiling apparatusincludes a fusion step (FIG./STEP) of fusing, as a new task, a task group including a reference task as a task having a conditional branch, and subsequent tasks as tasks control dependent, extended-control dependent, or indirect control dependent on respective of all branch directions of the conditional branch included in the reference task.

Parallel program generating method and parallelization compiling apparatus

A parallelization compiling method for generating a segmented program from a sequential program, in which multiple macro tasks are included and at least two of the macro tasks have a data dependency relationship with one another, includes determining an existence of invalidation information for invalidating at least a part of the data dependency relationship between the at least two of the plurality of macro tasks before compiling the sequential program into the segmented program, and generating the segmented program by compiling the sequential program into the segmented program with reference to a determination result of the existence of the invalidation information. When the invalidation information is determined to exist, the at least a part of the data dependency relationship is invalidated before the compiling of the sequential program into the segmented program.

Parallelization compiling method, parallelization compiler, and vehicular device

The present invention makes it possible to let a user arbitrarily and easily see any other scene than himself or herself in his or her view (the scene seen from any other moving body than him or her). In a display device (an image pickup and display deviceor a display device), specification information is generated to specify a specific image pickup device of outer image pickup devices (the image pickup and display deviceor and image pickup device), and image data are received from the image pickup device specified by the specification information and are displayed. As an outer image pickup device, for example, and image pickup device wore by some other person, image pickup devices set at a car, an electric train, and the like, or further mage pickup devices set at an animal, a bird, and the like are supposed. Image data picked up by these image pickup devices are transmitted to the display side and the image display is carried out in the display device. Thus, a user of the display device can see images of viewing scenes watched by other people, for example, images of viewing scenes seen from a car, an electric train, and the like, or images of viewing scenes seen from an animal, a bird, and the like.

Display apparatus for displaying image data received from an image pickup apparatus attached to a moving body specified by specification information

It is provided a processor system comprising at least one processor core provided on a semiconductor chip and including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes the task in a case of confirming that a flag indicating that the processor has completed predetermined processing has been written into the synchronization flag area; and stores the data subjected to the acceleration processing into the data area, and further writes a flag indicating that the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, the task corresponding to a flag in a case of confirming that the flag indicating the completion of the acceleration processing has been written into the synchronization flag area.

Processor, accelerator, and direct memory access controller within a core reading/writing local synchronization flag area for parallel

A parallelization compiling method for generating a segmented program from a sequential program includes assigning macro tasks included in the sequential program to cores included in the multi-core processor in order to generate the segmented program, adding a new macro task to the sequential program or deleting one of the macro tasks from the sequential program, and compiling the sequential program into the segmented program in response to the adding of the new macro task under a condition that the macro tasks assigned to the cores do not migrate among the cores or compiling the sequential program into the segmented program in response to the deleting of the one of the macro tasks under a condition that remains of the macro tasks assigned to the cores do not migrate among the cores.

In one or more embodiments, a method of generating a code by a compiler includes: analyzing a program executed by a processor; analyzing data necessary to execute respective tasks included in the program; determining whether a boundary of the data used by divided tasks is consistent with a management unit of a cache memory based on results of the analyzing; and generating the code for providing a non-cacheable area from which the data to be stored in the management unit including the boundary is not temporarily stored into the cache memory and the code for storing an arithmetic processing result stored in the management unit including the boundary into a non-cacheable area in a case where it is determined that the boundary of the data used by the divided tasks is not consistent with the management unit of the cache memory.

Method of providing a non-cacheable area in memory

It is provided a processor system comprising at least one processor core including a processor, a memory and an accelerator. The memory includes an instruction area, a synchronization flag area and a data area. The accelerator starts, even if the processor is executing another processing, acceleration processing and executes read instruction in a case where the read instruction is a flag checking instruction and a flag indicating the completion of predetermined processing has been written; and stores the data subjected to the acceleration processing after completion of the acceleration processing, and further writes a flag indicating the completion of the acceleration processing. The processor starts, even if the accelerator is executing another processing, read instruction corresponding to a flag in a case where the read instruction is the flag checking instruction and it is confirmed that the flag indicating the completion of the acceleration processing has been written.

Processor, accelerator, and direct memory access controller within a processor core that each reads/writes a local synchronization flag area for parallel execution

Image display system, image display apparatus, and image display method

A parallelizing compile method includes, dividing a sequential program for an embedded system into multiple macro tasks, specifying (i) a starting end task and (ii) a termination end task, fusing (i) the starting end task, (ii) the termination end task, and (iii) a group of the multiple macro tasks, extracting a group of multiple new macro tasks from the multiple new macro tasks fused in the fusing based on a data dependency, performing a static scheduling assigning the multiple new macro tasks to the multiple processor units, so that the group of the multiple new macro tasks is parallelly executable by the multiple processor units, and generating a parallelizing program. In addition, a parallelizing compiler, a parallelizing compile apparatus and an onboard apparatus are provided.

Parallelizing compile method, parallelizing compiler, parallelizing compile apparatus, and onboard apparatus

Image display system, display device and display method

According to some aspects, an image display apparatus is provided comprising a display apparatus comprising a display section and a controller. The controller may be configured to display a map image via the display section, set location specification information based on an input specifying a position on the map image, and transmit the location specification information to a server apparatus, receive image data transmitted from the server apparatus in response to the transmission of location specification information to the server apparatus, the received image data having been obtained by photographing by an imaging section of an imaging apparatus configured to be worn on a head of a user, and the received image data having been transmitted to the server apparatus from the imaging apparatus in addition to additional data comprising location information detected at a time when the image data was photographed.

Image display system, display apparatus, and display method

Provided is a multiprocessor system and a compiler used in the system for automatically extracting tasks having parallelism from an input program to be processed, performing scheduling to efficiently operate processor units by arranging the tasks according to characteristics of the processor units, and generating codes for optimizing a system frequency and a power supply voltage by estimating a processing amount of the processor units.

Multiprocessor system and multigrain parallelizing compiler

Growing community of inventors

Tokyo, Japan

Keiji Kimura