Canon Kabushiki Kaisha

Keiji Ishizuka

Toshihiko Ichise

Yuzo Kataoka

Hidekazu Takahashi

Hidefumi Ohsawa

Koji Aoki

Hayao Ohzu

Tetsuo Asaba

Toshiaki Sato

Tsutomu Ando

Tetsuya Tateno

Susumu Igarashi

Shunichi Kaizu

Atsushi Furuya

Shunichi Morita

A decoding apparatus which efficiently stores information to determine an address value to read a decoded value from a decoded value memory. The apparatus performs decoding processing at a high speed, and further, reduces the memory capacity. The apparatus comprises a first storage for continuously storing decoded values for variable-length codes of the same code length; a second storage for storing an initial address in the first storage; a third storage for storing offset values between the initial address in the first storage and addresses for storing decoded values for variable-length codes of respective code lengths, respectively; a first specification unit for specifying a code length of an input variable-length code; a second specification unit for specifying the order of the input variable-length code among variable-length codes belonging to the specified code length; and an address generator for generating an address to read a decoded value from the first storage, based on the offset value corresponding to the code length specified by the first specification unit and the order specified by the second specification unit.

Decoding apparatus and method

There is provided a coding apparatus and method for hierarchically coding an image, in which a number of consecutive lines of image data representing pixels of the image are entered line by line. Reduced image data representing pixels of a reduced image based on the entered image data are formed. A determination is made in parallel with the formation of the reduced image data as to whether or not image data of an object pixel to be coded can be predicted from the reduced image data and from image data representing surrounding pixels of the entered object pixel. The entered image data are coded in accordance with the determination result.

Coding method and apparatus therefor

Address information generated and output by an address converter for each pixel of input image data in accordance with the phase based on the position of the pixel to be coded is stored in an address storage divided into address groups which are periodically referred to. Information indicative of the occurrence probability of the pixel to be coded and phase information of the pixel are selectively output from the address storage, and an arithmetic coding is performed for the output. During the processing, update data is written in to one group while a read-out is being performed for the other group. A template is constituted by excluding a pixel which predeses one pixel, and a prediction state in each phase is divided into two parts. The template output is applied to both of the divided storage devices, and read actions are independently performed.

Coding/decoding apparatus and coding/decoding method

An image encoding device for effecting the carryover process on a real-time basis in arithmetic encoding, and without interruption in the function of the arithmetic encoder. The device is provided with an encoder for outputting code data, encoded by arithmetic codes, in succession by a predetermined number of bits, shift registers for retaining plural sets of the code data output from the encoder, and a processor for applying a carry-over process to the thus retained plural sets of code data.

Arithmetic encoding with carry over processing

A semiconductor device has a device region, and a device separation region formed on a semiconductor substrate doped with impurities. And, the device separation region has a metal wiring formed on the surface of the device region or the back surface of the substrate. An aluminum region extending in the longitudinal direction connected to the metal wiring is formed within the device separation region.

Device separation structure and semiconductor device improved in wiring

The present invention discloses a method and apparatus for hierarchical coding of image data using a typical prediction TP if a 2.times.2 array of pixels can be reduced to coded pixel. The present invention uses a TP flag, TP discrimination and a two line delay. Accordingly, the hierarchical coding can be realized by a small amount of hardware. According to deterministic prediction DP, if there is a decision that the image data may be reduced then the value of the pixel can be predicted from a reduced pixel (low resolution data) and surrounding pixels (high resolution data) which are extracted in advance. If the pixel to be coded is one that can be uniquely determined this pixel is excluded form coding.

A driver circuit comprises a current mirror circuit including an output transistor, a load connected to a main electrode of the output transistor, and current supplying device for supplying a current to a control electrode of the output transistor. The output transistor controls a current flowing through the load.

Semiconductor light emitting element driver circuit

A circuit device including a DC characteristic test circuit is arranged to have a reset signal supplied via a reset signal input terminal for resetting a testee circuit to be subjected to a DC characteristic test; and to include an output buffer circuit which receives a predetermined output signal of the testee circuit and the reset signal supplied from the reset signal input terminal. The arrangement enables the DC characteristic test to be quickly carried out on the circuit device at a low cost and without increasing the number of terminals required for the test.

Circuit device having a test function for checking circuit operation

A semiconductor device including a bipolar transistor, has a collector region including a first semiconductor region of the first conductivity type and a second semiconductor region of the first conductivity type having higher resistance than the first semiconductor region, a base region including a semiconductor region of the second conductivity type, and an emitter region including a semiconductor region of the first conductivity type. The semiconductor device further comprises a metal layer region for connecting the first semiconductor region and the collector electrode on the collector region provided within the second semiconductor region layer of the collector region.

Method of making a semiconductor device with buried electrode

Semiconductor device with buried electrode

An image signal correcting circuit device includes an A/D conversion unit for converting an analog image signal output from an image reading unit into a digital signal, a storage unit for storing correction data, and a correction unit for performing correction on a signal based on the correction data stored in the storage unit. The correction data stored in the storage unit is difference data between at least two pixel signals in the digital signal which is generated by a correction data generating unit. Alternatively, the correction data stored in the storage unit is obtained by amplifying an analog reference signal by an amplification factor of m (m&gt;1) and by converting the amplified analog signal into a digital correction signal by the A/D conversion unit.

Image signal correcting in image data processing requiring only small

Semiconductor device with isolating groove containing single crystalline

A differential phase shift keying demodulator for demodulating a signal modulated by differential phase shift keying is arranged to compare the modulated signal with a delayed modulated signal at different points of time within a period required for transmitting one bit of data.

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Kawasaki, Japan

Keiji Ishizuka