Hitachi, Ltd.

Nissan Motor Company Limited

Keiji Hideshima

Masaoki Takaki

Kazuyoshi Asada

Haruo Koyanagi

Isao Yasuda

Kunio Yamanaka

Hiroharu Suda

Hirokazu Sawano

Naoki Sasaki

Norio Murayama

Yoshiyuki Nihashi

Shuichi Senda

Atsutaro Kamei

Novel method and system for controlling input/output in a process control wherein state signals of object processes to be controlled are applied to a CPU via a process input/output unit and operated in the CPU in accordance with a logic programmed and stored in advance, and results of the operation are delivered out to the object processes to control the same. A buffer memory is interposed between the CPU and the process input/output unit. While reception and delivery of data are performed between the CPU or processor unit and the buffer memory, fetching of the state signals of the object processes or delivery of the process controlling signals is performed between the buffer memory and the object processes, thereby attaining a high rate processing as viewed from the overall processing of the system.

Method and system for controlling input/output in process control

A sequence control system includes a main memory unit for storing therein a sequence program, an operation and control unit for decoding the sequence instruction and executing the designated operations, an input unit for fetching states of a process to be controlled as inputs, and an output unit for producing an output signal to control the process.

Programmable sequence controller

A programmable sequence controller is provided with a display signal processor for preparing and correcting a sequence program in combination with a CRT (or cathode ray tube) display device. The signal processor simply effects signal processing of branch points and composition points in case where a so-called 'ladder diagram' constituting the sequence diagram with relay symbols is prepared and displayed. Branch information is stored in an FIFO (or first in first out) register. The branch information is sequentially received and stored, and the information thus stored is read out in the order of storage, thus preparing the ladder diagram. There are provided a register for instructing the FI operation and a register for instructing the FO operation. The sequence display controller is applicable to the cases where a new ladder diagram is to be prepared, the diagram once prepared is corrected, and the operation is checked.

Sequence display controlling method and controller

A sequence control system suitable for checking the operation of an information processor includes a process I/O unit for receiving input data from process inputs and providing output data to process outputs; a sequence processing unit for calculating data at the process outputs by performing sequence operations according to the sequence programs stored in a sequence program memory on the basis of the data at the process inputs; a buffer memory provided between the process I/O unit and the sequence processing unit for storing both the process input data from the process I/O unit and the output data from the sequence processing unit; a control arrangement for setting the input data to the buffer memory and for allowing access to a selected sequence program according to manually set input information; a display for displaying the selected sequence program accessed through the control arrangement; and a switch for interrupting the transfer of I/O data between the process I/O unit and the buffer memory. The sequence processing unit determines the output data on the basis of the input data stored in the buffer memory and applies the output data to the buffer memory. The control arrangement, in response to the manually set input information, causes the associated sequence program to be read from the sequence program memory and then the data of the inputs and outputs associated with the sequence program to be read from the buffer memory thereby to indicate them on the display.

Sequence control system

A method and an apparatus for diagnosing a fault in a sequence control system performing control in accordance with a predetermined sequence, wherein memory means having bits corresponding to respective ones of a plurality of predetermined sequence steps is provided. The sequence of steps actually applied to an object to be controlled are sequentially stored in corresponding bits. Each time a sequence step is applied to the object to be controlled, the contents of the memory means are checked to see whether or not any of the sequence steps applied thus far have been skipped. If any sequence step has been skipped, a fault is determined. Preferably, a fault is also determined when any of the intervals of sequence steps successively applied exceeds a predetermined length of time. Upon determination of a fault, the sequence step associated with the fault is identified, and the control circuit associated with the sequence step in fault is preferably displayed.

Fault diagnosis apparatus and method for sequence control system

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Fujisawa, Japan

Keiji Hideshima