Fujitsu Corporation

Keiichiro Uchida

Shigeru Nagasawa

Minoru Koshino

Tetsuro Okamoto

Masanori Motegi

Takatoshi Muraoka

Shigeaki Okutani

Hiroshi Tamura

Yoshiyuki Tanakura

An information processing system including an arithmetic unit in which one unit of data is processed according to a corresponding one instruction, and another arithmetic unit in which a great amount of data are processed according to a corresponding instruction. Also included is an instruction controller which distributes instructions selectively to respective arithmetic units (12) and a main storage (12) which achieves two-way data communication with the arithmetic units. In the system synchronization is performed with respect to instructions, among the aforesaid instructions, which, above all, must be executed in respective fixed execution sequences, by utilizing a newly employed synchronization instruction. Further, the aforesaid instructions are classified, in dependence upon the execution sequence, into first instructions which are to be executed under a serial processing mode and second instructions which can be executed under a parallel processing mode, by inserting both a serialized-starting instruction (POST) and a serialized-releasing instruction into the aforesaid instructions.

Vector data processing system with instruction synchronization

In an information processing unit, in particular, in a data flow type information processing unit, an instruction indicates whether operand data for use by this instruction is available. Operand data, both from external storage units and from previously executed instructions, are stored in a data memory while instructions are stored in an instruction memory. An instruction execution unit is started by a control signal when all operands necessary for executing an instruction are available. Instructions and data can be routed independently, thereby permitting more rapid execution of instructions.

Data processing unit utilizing data flow ordered execution

The present invention discloses a data processing system where a plurality of vector registers consisting of plurality of elements are provided between a main memory unit and an operational processing unit, the desired data is transferred to the vector registers from the main memory unit and is held therein, and various processings such as a logical operation are carried out by sequentially accessing the elements within said vector registers. The present invention also includes a plurality of memory banks which can be independently accessed and are provided for the vector registers. A series of elements of each vector register are interleaved in the plurality of memory banks and the elements having the same numbering in each vector register are arranged in the same memory bank. Timing necessary for starting access to a series of elements of said vector registers are specified for each class of processing, so that the vector operation processings can be done very effectively and without operand collision.

Bank interleaved vector processor having a fixed relationship between

A memory access control system in a vector processing system comprises a memory unit, a memory device, address holding registers, a shift register and data buffer registers. The memory access control system distinguishes each vector data read out from the memory unit based upon the address holding registers by the output of the shift register. The shift register stores vector element numbers indicated by the memory device and transfers same to the data buffer registers. Each number from 0 to n-1, of a vector A composed of n elements a.sub.0, a.sub.1, a.sub.2, . . . a.sub.n-1, is a vector element number and each data, from a.sub.0 to a.sub.n-1, is vector element data.

Memory access control system in vector processing system

A data processing system having a pipeline processing architecture for performing a sequence of operations upon each group of data, one of which is a conditional group, comprising a main pipeline for performing the sequence of operations upon the data other than the conditional data and a sub-pipeline for processing the conditional data, wherein the two pipelines are synchronized on the same time base so that executing time is determined only by the main pipeline.

Data processing system having a high speed pipeline processing

A system for controlling the addition of signed binary numbers represented with N bits, of the 2's complement notation, is disclosed which includes addend and augend sign control circuits, and an adder circuit comprising a carry save adder and a carry proper gate adder. The addend sign control circuit receives an operation command sign signal (B, --B, .vertline.B.vertline. or --.vertline.B.vertline.) for the addend, which designates the addend of the certain type (B, .vertline.B.vertline. or --.vertline.--B.vertline.) to be applied directly to the carry save adder and designates the addend of another type (--B, .vertline.--B.vertline. or --.vertline.B.vertline.) to be applied to the carry save adder through a 1's complementer. The augend sign control circuit functions similarly for the augend being applied to the carry save adder. A corrective number (0, 1 or 2) is applied to the adder circuit which corresponds to neither, one, or both the addend and augend being applied to the adder circuit through their respective 1's complementer.

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Kawasaki, Japan

Keiichiro Uchida