Oki Electric Industry Co., Ltd.

Keiichiro Takeda

Teruhiro Harada

Shooji Kitazawa

Hitoshi Kokubun

Yuichi Ashizawa

A nonvolatile semiconductor memory comprises a cell bias circuit supplying a first voltage, a memory cell array having memory cell transistors, word lines, drain lines disposed perpendicular to the word lines and source lines disposed perpendicular to the word lines. the nonvolatile semiconductor memory further comprises source line equalizing transistors connected between the cell bias circuit and the source lines, respectively, the source line equalizing transistors turning on during a stand by mode, drain line equalizing transistors connected between the cell bias circuit and the drain lines, respectively, the drain line equalizing transistors turning on during the stand by mode, bit lines, main source lines, source line selecting transistors connected between the main source lines and the source lines, respectively, the source line selecting transistors turning off during the stand by mode, drain line selecting transistors connected between the bit lines and the drain lines, respectively, the drain line selecting transistors turning off during the stand by mode and a detecting circuit connected to said bit lines for supplying the first voltage to the bit lines for detecting data stored in the memory cells.

Nonvolatile semiconductor memory circuit capable of high-speed data reading

A non-volatile semiconductor memory decreases a parasitic current as much as possible without using an electric separation means. This nonvolatile semiconductor storage apparatus has multiple memory cells rows having multiple memory cell transistors M,M,. . . whose gates are connected to word lines WL,, WL,. . . , respectively, and whose sources and drains are serially connected. This non-volatile semiconductor storage apparatus also has multiple column lines SBL,SVL,SVL,SBL,. . . which connect the connection nodes between the sources and drains of the memory cell transistors M,M,. . . in the column direction, a power source line PV,which supplies a prescribed electric potential to these column lines, first and second sense amplifiers which detect the electric potential level of the column lines or a current that flows through the column lines, sense column line selection means SS,SS,SS,SS,and,which connect column lines SBL,and SBL,connected to one terminal of selected memory cell M,and one terminal of selected memory cell M,respectively, to the first and second sense amplifiers A,and A,respectively. In this case, the memory cell M,is separated from the memory cell M,by a prescribed number of memory cells on the same memory cell row. This nonvolatile semiconductor storage apparatus further has power source supply column line selection means DS,DS,DS,DS,. . . which connect the column lines connected to the other terminals of the two selected memory cells to the power source line.

Non-volatile semiconductor memory capable of reducing parasitic current

A synchronous semiconductor burst nonvolatile semiconductor memory includes first and second address counter circuits and a counter selection circuit in order to output an address signal to a first latch circuit for storing therein data from a memory cell. Either the first address counter circuit or the second address counter circuit is alternately selected by the counter selection circuit in response to a burst control signal. According to the invention, either the first address counter circuit or the second address counter circuit is always selected, and a burst address signal is outputted to the latch circuit on the basis of an externally supplied address signal (first signal of the burst address signal) before the burst control signal is generated.

Growing community of inventors

Tokyo, Japan

Keiichiro Takeda