Spansion Llc.

Keiichiro Kikuchi

Hiroaki Wada

Norihiko Yamaki

A memory that employs a redundant cell array for recovery of one or more failed core cell arrays of multi-bit memory cells is described. The memory includes a plurality of core cell arrays, at least one redundant cell array, and a memory controller. The memory controller is configured to dynamically assign the redundant cell array to a failed core cell array when erasing at least a portion of the plurality of core cell arrays. The memory controller is further configured to provide read/write access to the redundant cell array when the failed core cell array is selected for read/write access.

Memory employing redundant cell array of multi-bit cells

The invention is a semiconductor device that includes a memory cell array having non-volatile memory cells, and a control circuit that writes data into the memory cell array by programming memory cells to be programmed to a first level and then programming the memory cells to a second level, and its control method. According to the present invention, the time necessary for writing data can be reduced by shortening the time for programming to the first level. Further, a required data retention time can be secured by programming to the second level.

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Kitakata, Japan

Keiichiro Kikuchi