Renesas Technology Corp.

Hitachi, Ltd.

Hitachi Ulsi Systems Co., Ltd.

Seikagaku Corporation

Other

Hitachi Ulsi Engineering Corp.

Seikagaku Kogyo Kabushiki Kaisha

Nec Corporation

Synaptics Corporation

Konami Co., Ltd.

Hitachi Device Engineering Co., Ltd.

Konami Corporation

Seikagaku Kogyo Kabushiki Kaisha (seikagaku Corporation)

Seikagaku Kogyo Co. Ltd.

Keiichi Yoshida

Atsushi Nozoe

Shoji Kubono

Yoshinori Takase

Takayuki Kawahara

Hiroshi Sato

Hideaki Kurata

Michitaro Kanamitsu

Katsutaka Kimura

Hiroaki Kotani

Satoshi Noda

Ken Matsubara

Takashi Horii

Shooji Kubono

Akira Tawada

Kiyoshi Morikawa

Hiroshi Maruyama

Tetsuya Tsujikawa

Tomoyuki Fujisawa

Satoshi Miyauchi

Masayuki Ishihara

Saburo Hara

Naoki Kobayashi

Takashi Kobayashi

Takayuki Tamura

Shunichi Saeki

Akira Asari

Tsutomu Nakajima

Shinji Yuasa

Hirofumi Miyazono

Toshihiro Tanaka

Yoshinobu Nakagome

Hitoshi Kume

Takashi Yamaguchi

Masataka Kato

Hiroshi Shimura

Takayuki Noto

Tomoharu Kiyuna

Masahiko Kuroda

Kenji Okajima

Masaaki Shiomura

Hirokazu Hatayama

Tomohiro Hirakawa

Junichi Onaya

Hiroaki Torii

Mamoru Kyogashima

Yoichi Okuda

Yoriaki Miyoshi

Junichi Sasa

Koichi Ozaki

Hiroshi Kikuchi

Ken' Ichi Kamijo

Ken-ichi Maeyama

Kiyoshi Mukai

Mikio Arai

Akikazu Takada

A processing system includes a timing controller and source driver circuitry. The timing controller is configured to stop scanning of a plurality of gate lines of a display panel in response to a detection of a communication failure between the processing system and a controller. The source driver circuitry is configured to update a plurality of display elements of the display panel to cause a black display in response to expiration of a time limit after the detection of the communication failure. The timing controller may be further configured to resume the scanning of the plurality of gate lines in response to the expiration of the time limit.

Device and method for driving a display panel

A method of evaluating a cell state based on information of an image taken of a cell containing a chromosome territory is provided. This method includes extracting the chromosome territory from the image (S), standardizing a positioning state of the chromosome territory and then quantifying the positioning state (S), and evaluating the cell state based on the quantified positioning state of the chromosome territory (S).

Method of evaluating chromosome state and evaluation system

A non-volatile storage device () has non-volatile memory units (FARYto FARY), buffer units (BMRYto BMRY) and a control unit (CNT), and the control unit can control a first access processing between an outside and the buffer unit and a second access processing between the non-volatile memory unit and the buffer unit upon receipt of directives from the outside separately from each other. The control unit can independently carry out an access control over the non-volatile memory unit and the buffer unit in accordance with the directives sent from the outside, respectively. Therefore, it is possible to set up next write data to the buffer unit simultaneously with the erase operation of the non-volatile memory unit or to output once read storage information to the buffer unit at a high speed as in a cache memory operation in accordance with the directive sent from the outside. Consequently, it is possible to reduce the overhead of a data transfer for reading/writing data from/to the non-volatile storage device.

Non-volatile memory having multiple erase operations

A flash memorybased on the multilevel storage technology for storing the information of two or more bits is provided with four banksto. For example, in the left side of the bank, a data latchis provided along one short side of the bank, while in the right side thereof, a data latchis provided along the other short side of the bank. At the lower side of the data latches, arithmetic circuitsare provided. The data latchesare respectively formed of SRAMs. A sense latchis divided to one half in the right and left directions with reference to the center of sense latch row. The divided sense latchis connected with the data latchesvia the signal lines respectively allocated along both short sides of the bank

Nonvolatile semiconductor storage device

A nonvolatile memory device of the present invention performs a programming operation by accumulating a charge in certain capacitance which is provided for each programming memory cell and injecting hot electrons generated when the charge is discharged via the memory cell into a floating gate. Thus, a variation in a programming characteristic of the nonvolatile semiconductor memory device is reduced, thereby realizing high-speed programming operation.

Nonvolatile memory with independent access capability to associated buffer

A memory system includes a plurality of nonvolatile memory chips (CHPand CHP) each having a plurality of memory banks (BNKand BNK) which can perform a memory operation independent of each other and a memory controller () which can control to access each of said nonvolatile memory chips. The memory controller can selectively instruct either a simultaneous writing operation or an interleave writing operation on a plurality of memory banks of the nonvolatile memory chips. Therefore, in the simultaneous writing operation, the writing operation which is much longer than the write setup time can be performed perfectly in parallel. In the interleave writing operation, the writing operation following the write setup can be performed so as to partially overlap the writing operation on another memory bank. As a result, the number of nonvolatile memory chips constructing the memory system of the high-speed writing operation can be made relatively small.

Memory system and memory card

Optimized layout for multi-bit memory banks each with two data latches and two arithmetic circuits

A nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array configuration in which a plurality of pages correspond to and are connected to each of a plurality of word lines and higher speed of the erasing operation. In a flash memory, the erasing operation is performed by an erasing method of erasing a plurality of pages arbitrarily selected in a lump. In a two-page erasing mode, page erasure, page pre-erasure verification, page rewriting process, page pre-rewriting verification, and page upper end determining process are performed in order. The method realizes, particularly, (1) suppression of the number of erase verification times to the minimum by performing erase verification only on arbitrary one even-numbered or odd-numbered page in the pages to be erased in consideration of variations in the erasing characteristic, and (2) prevention of erroneous determination of the upper end of erasure since it is unnecessary to set a memory cell to be rewritten every rewrite verification by continuously executing the rewriting process page by page.

Nonvolatile semiconductor memory device capable of realizing optimized erasing operation in a memory array

The disclosed flash memory is provided with a majority logic circuitand shift registersto. Three out of the bankstoof the memory respectively include management information areas KAs to store binary management information comprising power supply trimming data and bitline restoration data. During initialization of the flash memory, the majority logic circuitperforms error correction on management information bits retrieved from the management information areas KAs and outputs that information to a trimming/restoration data buffer, thus providing highly reliable management information very quickly. The shift registerstodelay a control signal that is output from a control circuitby a certain period of time before outputting the control signal to sense amplifiersto. This delay makes it possible to make the operating currents of the bankstostart to flow at different times and to suppress a peak current flowing in the flash memory.

There is provided a method of programming a non-volatile memory which can solve the problem of the data write system of the existing flash memory that a load capacitance of bit lines becomes large, the time required by the bit lines to reach the predetermined potential becomes longer, thereby the time required for data write operation becomes longer and power consumption also becomes large because the more the memory capacitance of memory array increases, the longer the length of bit lines becomes and the more the number of bit lines increases. In the non-volatile memory of the invention comprising the AND type memory array in which a plurality of memory cells are connected in parallel between the local bit lines and local drain lines, the local drain lines are precharged by supplying thereto a comparatively higher voltage from the common drain line side (opposite side of the main bit lines), the main bit lines are selectively precharged by applying thereto the voltage of 0V or a comparatively small voltage depending on the write data and thereafter a drain current is applied only to the selected memory cells to which data is written by applying the write voltage to the word lines in order to implant the hot electrons to the floating gate.

Nonvolatile memory and method of programming the same memory

This is a nonvolatile semiconductor memory device capable of raising the speed of write operation of Y access circuits in a 1&#xd7;sense latch circuit+2&#xd7;SRAM configuration. In a multi-value flash memory, in a mode of writing from the lower voltage side, writing and erratic determination are performed after data are transferred from SRAMs to a sense latch circuit for '10' and '00' distributions; after the data transfer for &#x201c;01&#x201d; distribution, writing is done; after the data transfer for &#x201c;11&#x201d; distribution word disturb determination is done; and simplified upper limit determination is done in this sequence. In particular by (1) writing from the lower voltage side of the threshold voltage distribution in the multi-value memory and (2) consecutive application of &#x201c;write processing&#x201d; and &#x201c;upper limit determination processing&#x201d; to each threshold voltage distribution, after the end of write processing for &#x201c;10&#x201d; and &#x201c;00&#x201d; distribution, since the threshold voltages of all the memory cells are lower than the upper limit determination voltages of the &#x201c;10&#x201d; and &#x201c;00&#x201d; distributions, no transfer of write data is needed in upper limit determination processing because other threshold voltage distributions are not masked.

Nonvolatile semiconductor memory device

Growing community of inventors

Musashimurayama, Japan

Keiichi Yoshida