Shin-etsu Handotai Co., Ltd.

Keiichi Okabe

Tadahiro Kato

Hisashi Oshima

Sadayuki Okuni

Tokio Takei

Susumu Miyazaki

Takao Abe

Hisakazu Takano

Daisuke Nakamata

Shunichi Ikeda

Hajime Miyajima

Takao c/o Shin-Etsu Handotai Co Ltd Abe

The present invention provides a method for manufacturing a bonded wafer comprising steps of forming an oxide film on at least a surface of a base wafer or a surface of a bond wafer; bringing the base wafer and the bond wafer into close contact via the oxide film; subjecting these wafers to a heat treatment under an oxidizing atmosphere to bond the wafers together; grinding and removing the outer periphery of the bond wafer so that the outer periphery has a predetermined thickness; subsequently removing an unbonded portion of the outer periphery of the bond wafer by etching; and then thinning the bond wafer so that the bond wafer has a desired thickness, wherein the etching is conducted by using a mixed acid at 30&#xb0; C. or less at least comprising hydrofluoric acid, nitric acid, and acetic acid. Thus there is provided a method for manufacturing a bonded wafer by which unbonded portions of the outer periphery of the bond wafer are removed with a high selectivity ratio (R/R) without causing metallic contamination.

Method for manufacturing bonded wafer

The present invention provides a method for evaluating nanotopography of a surface of a semiconductor wafer sliced from a semiconductor ingot, the method being conducted prior to polishing of the surface, the method at least comprising: measuring a surface profile of the wafer in the direction that the wafer is sliced; determining a maximum inclination value of warp change of the wafer surface in a sectional profile in the direction that the wafer is sliced of the measured surface profile; and estimating nanotopography of the wafer surface after being polished based on the determined maximum value. As a result, there are provided a method and an apparatus for evaluating nanotopography of a surface of a semiconductor wafer, and a method for manufacturing a semiconductor wafer exhibiting good nanotopography level on the surface.

Method for evaluating semiconductor wafer, apparatus for evaluating semiconductor wafer, and method for manufacturing semiconductor wafer

The present invention provides a method for manufacturing a bonded wafer, which includes at least the steps of bonding a bond wafer and a base wafer, grinding an outer peripheral portion of the bonded bond wafer, etching off an unbonded portion of the ground bond wafer, and then reducing a thickness of the bond wafer, wherein, in the step of grinding the outer peripheral portion, the bonded bond wafer is ground so as to form a groove along the outer peripheral portion of the bond wafer to form an outer edge portion outside the groove; and in the subsequent step of etching, the outer edge portion is removed together with the groove portion of the bond wafer to form a terrace portion where the base wafer is exposed at the outer peripheral portion of the bonded wafer. Thus, it is possible to provide a method for manufacturing a bonded wafer, which can reduce the number of dimples formed in a terrace portion of a base wafer upon removing an outer peripheral portion of a bonded bond wafer.

Method for manufacturing bonded wafer and outer-peripheral grinding machine of bonded wafer

Production method for silicon wafer and SOI wafer, and SOI wafer

A method for producing a semiconductor wafer that yields a wafer having high flatness and back surface characteristics to address problems concerning the back surface of a wafer produced by the conventional surface grinding/double side polishing method and observed during the production process. The method comprises flattening both sides of the wafer by surface grinding means, eliminating a mechanically damaged layer by an etching treatment, and then subjecting a front surface of the wafer to a single side polishing treatment, wherein a back surface of the wafer has glossiness in a range of 20-80%.

Semiconductor wafer and production method therefor

A surface grinding method is provided by which grinding striations are produced so that the striations can fully be removed by a polish-off amount less than required in a conventional way in mirror polishing following surface grinding using an infeed type surface grinder, in which two circular tables, opposite to each other, which are driven and rotate independently from each other, are arranged so that the peripheral end portion of one table coincides with an axial center of a rotary shaft of the other table all time, the two circular tables being located so as to be shifted sideways from each other; not only is a grinding stone held fixedly on an opposite surface of the one table, but the wafer is fixed on an opposite surface of the other table; the two tables are rotated relatively to each other; and at least one table is pressed on the other while at least one table is relatively moved in a direction, so that a surface of the wafer is ground, wherein the surface of the wafer is ground while controlling a pitch of grinding striations produced across all the surface of the wafer processed by the grinding stone to be 1.6 mm or less.

Processing method for a wafer

The present invention has an object to provide a manufacturing process of a semiconductor wafer in which improvement on accuracy in a chamfering portion is realized. The manufacturing process of a semiconductor wafer comprises: a slicing step of obtaining a wafer in the shaped of a thin disk by slicing a single crystal ingot; a surface-grinding step of flattening a surface of the wafer; a chamfering step of chamfering the peripheral edge portions; and mirror-polishing step of mirror-polishing the surface of the wafer, wherein a simultaneous double-side surface-grinding step of grinding both sides of the wafer simultaneously by a double-side grinding machine is existent prior to the chamfering step in order to remove wafer waviness and a secondary grinding step is performed by grinding a single side or simultaneously both sides of the wafer after the chamfering step is carried out, so that improvement on accuracy in a chamfered portion is realized.

Manufacturing process for semiconductor wafer

The present invention provides a surface grinding method and apparatus for achieving a thin plate work such as a semiconductor wafer with high flatness, high accuracy and certainty and the apparatus comprises: a surface grinder in which a grinding wheel support member,by which a rotary shaft,of a grinding wheel,is supported is held by a pivotal shaft portion,and a grinding wheel shaft inclination control motor,which displaces the grinding wheel support member,by activating the pivotal shaft portion,is provided; a corrective angle storage device,which stores a corrective angle of an inclination angle of a rotary shaft,of the grinding wheel,to a rotary shaft,of a wafer,; and a shaft inclination control apparatus,which sends out a signal to control the grinding wheel shaft inclination control motor,while reading a corrective angle of the corrective angle storage device,, wherein a relative inclination angle of the grinding wheel to the thin plate work, in a more concrete manner an inclination angle of the rotary shaft,of the grinding wheel,, is changed for each of grinding steps of high rate feed, low rate feed and spark-out.

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Nagano, Japan

Keiichi Okabe