Nec Corporation

General Electric Company

Keiichi Ohata

Kenichi Maruhashi

Masaharu Ito

Hikaru Hida

Masaki Ogawa

Takao Morimoto

Yasuhiro Hamada

Kazuhiro Ikuina

Shuya Kishimoto

Akihiko Okamoto

Kensuke Kasahara

Toshio Baba

Takeya Hashiguchi

Tomohiro Itoh

Masaharu Itou

Shuuya Kishimoto

The present invention intends to improve communication efficiency between two communication apparatuses each engaged in the communication by full duplex communication method by using a surplus band of the one to transmission band of the other. A first bandwidth required by a first communication apparatus (A) at data transmission and a second bandwidth required by a second communication apparatus (B) at data transmission are presumed. Next, the first bandwidth presumed as mentioned is compared to a first bandwidth used which the first communication apparatus (A) currently uses and at the same time, the second bandwidth presumed as mentioned is compared to a second bandwidth used which the second communication apparatus (B) currently uses. The first bandwidth and the second bandwidth are then adjusted, and a third bandwidth which the first communication apparatus (A) uses at data transmission and a fourth bandwidth which the second communication apparatus (B) uses are determined.

Band control method and communication apparatus

A balun circuit includes a first CPW line, a second CPW line, and a third CPW linethat serve as signal input/output ports; a first CPS linethat is a differential transmission line, the first CPS linerelaying the first CPW lineto the second CPW line; a second CPS linethat is a differential transmission line, the second CPS linerelaying the first CPW lineto the third CPW line; and at least one connection section that connects grounded conductors of each of the first CPW line, the second CPW line, and the third CPW line

Balun circuit and integrated circuit device

An oscillator comprising a dielectric resonator (DR) has a high controllability and reproducibility of coupling between the dielectric resonator (DR) and an oscillation circuit, and an integrated circuit is reduced in size. The dielectric resonator (DR) () is composed of a dielectric substrate (), grounding conductive layers () formed on both sides of the dielectric substrate (), and via holes () for electrical connection between the conductive layers. A coupling element () composed of a slot () provided in the central portion of the grounding conductive layer () and a patch () surrounded by the slot () is coupled to the dielectric resonator (DR) (). The patch () is connected to a transmission line () on an oscillation circuit () through a bump (). The transmission line () is connected to the ground through a termination resistor (). On the oscillation circuit MMIC (), the transmission line () is connected to the gate of a transistor FET () A capacitive transmission line () for positive feedback is connected to the transistor FET (). The output of the transistor FET () is connected to a transmission line () for output through a matching circuit (). The transmission line () is bump-connected to a coplanar line () composed of a signal conductive layer () formed on an edge of the dielectric resonator (DR) () and the grounding conductive layer ().

Dielectric resonator, dielectric resonator frequency adjusting method, and dielectric resonator integrated circuit

The present invention provides a filter exhibiting excellent filter characteristics and having less number of stages. A dielectric substrate () has one surface connected to a top conductor () and an opposite surface connected to a bottom conductor (). A pair of rows of via-holes connecting together the top conductor () and the bottom conductor () are formed along the signal transfer direction. A slit () is formed in a portion of the top conductor () overlying the central resonator among a plurality of resonators. The slit () extends in a direction perpendicular to the signal transfer direction. Slits () are formed in each of portions of the top conductor () overlying resonators disposed at both ends. A coplanar waveguide () mounted on the top conductor () is connected to the slit ().

Dielectric waveguide filter with inductive windows and coplanar line coupling

A conductive layer is formed on each of the upper and lower surfaces of a dielectric substrate, and the two conductive layers are connected by rows of via-holes that are formed which a spacing that is less than or equal to &#xbd; of the wavelength in the dielectric substrate in the resonance frequency, whereby n stages of dielectric resonators and input/output waveguide structures are formed. If the number n of stages is assumed to be 3, the first-stage resonator and the second-stage resonator are coupled by an electromagnetic field by means of via-holes of a first spacing; the second-stage resonator and the third-stage resonator are coupled by an electromagnetic by means of via-holes of a second spacing, whereby a filter is formed. The input/output waveguide structure and the filter are coupled by an electromagnetic by means of via-holes of a fourth spacing. The first-stage resonator and the third-stage resonator are coupled by an electromagnetic field by means of via-holes of a third spacing.

Dielectric waveguide filter

A dielectric waveguide tube band-pass filter assuming lower characteristic change upon mounting, and having smaller dimensions and lower loss. Conductor layers () are formed on the top and bottom surfaces of a dielectric substrate (), wherein the top conductor layerand the bottom conductor layerare connected together through via-holes (). The via-holes () are formed in at least two rows along the signal transfer direction. In the dielectric waveguide tube configured by the top and bottom conductor layers () and the via-holes (), via-holes () are arranged in the signal transfer direction at spacing equal to or below &#xbd; of the in-tube wavelength to thereby configure resonators. The dielectric band-pass filter is configured by coupling adjacent resonators together through the via-holes () configuring inductive windows. On the surface of the dielectric substrate (), a co-planar line () including the conductor layer () as the ground and the conductor layer (2) as a signal conductor is configured so as to overstride the inductive windows configured by the via-holes ().

A high frequency circuit substrate comprises a first high frequency circuit substrate including at least a first dielectric material layer, a first conductor layer, a second dielectric material layer and a second conductor layer, which are laminated in the named order, the first conductor layer having a first slot formed therein, and the second conductor layer forming a transmission line, the first dielectric material layer having a first opening exposing the first slot at its bottom. The high frequency circuit substrate also comprises a second high frequency circuit substrate including at least a third dielectric material layer, a third conductor layer, a fourth dielectric material layer and a fourth conductor layer, which are laminated in the named order, the third conductor layer having a second slot formed therein, and the fourth conductor layer forming a transmission line, the third dielectric material layer having a second opening exposing the second slot at its bottom. The first high frequency circuit substrate and the first high frequency circuit substrate are bonded to each other in such a manner that the first dielectric material layer and the third dielectric material layer are faced to each other and the first slot and the second slot are electromagnetically coupled, by inserting one side and the other side of a conductor plate having a through hole into the first opening and the second opening, respectively.

High frequency circuit substrate and method for forming the same

An RF package includes a multilayered dielectric substrate, a feed-through, and metal members. First and second dielectric substrates are formed on the multilayered dielectric substrate. The multilayered dielectric substrate has a cavity where a semiconductor element is to be mounted. The feed-through connects the inside and outside of the cavity and is comprised of a coplanar line formed on the first dielectric substrate and an inner layer line obtained by forming the second dielectric substrate on the coplanar line. The coplanar line and the inner layer line share a strip-like signal conductor. The metal members are formed at a connection interface between the coplanar line and the inner layer line on two sides of the signal conductor.

RF package with multi-layer substrate having coplanar feed through and connection interface

A multi-layer substrate comprises a first dielectric layer, a coplanar waveguide line formed on a first surface of the first dielectric layer, the coplanar waveguide line including a signal conductor and a pair of ground conductor layers positioned at opposite sides of the signal conductor, separately from the signal conductor, and a second dielectric layer formed to cover the coplanar waveguide line and the first dielectric layer and having an opening positioned at least on the signal conductor of the coplanar waveguide line. A thickness of the first dielectric layer is smaller than the value of c/&lcub;4f&middot;(&isin; &minus;1) &rcub;, where c is velocity of light, f is a frequency of a signal propagating in the signal line, and &isin; is a dielectric constant of the first dielectric layer.

Multi-layer substrate suppressing an unwanted transmission mode

The present invention provides a transmission line structure comprising: a dielectric substrate having first and second surfaces; a signal conductive layer selectively provided on the first surface of the dialectic substrate for signal transmission; at least a first non-signal conductive layer being selectively provided on the first surface of the dialectic substrate, and the at least first non-signal conductive layer being separated from the signal conductive layer; and a second non-signal conductive layer being provided on the second surface of the dialectic substrate, wherein the dielectric substrate has at least a conductive region extending in contact with only one of the at least first non-signal conductive layer and the second non-signal conductive layer so that the at least conductive region is separated by the dielectric substrate from remaining one of the first non-signal conductive layers and the second non-signal conductive layer in view of a vertical direction to the first and second surfaces of the dielectric substrate.

Coplanar transmission line

A substrate-type non-reciprocal circuit element comprises a substrate, a ferrite embedded in the substrate, a central electrode formed on the ferrite at one principal surface of the substrate, a plurality of signal conductors formed on the one principal surface of the substrate to extend from the central electrode into a plurality of different outward directions, a first ground electrode formed on the one principal surface of the substrate, separately from the central electrode and the plurality of signal conductors, and a second ground electrode formed on the other principal surface of the substrate and electrically connected to the first ground electrode. Thus, the substrate-type non-reciprocal circuit element can be easily electrically connected to a measurement machine, to enable to precisely and easily measure an electrical characteristics with a good repeatability. In addition, the substrate-type non-reciprocal circuit element can be connected to an electric circuit such as a receiver circuit and a transmitter circuit with a low transmission loss and a low variation in the transmission loss.

Substrate-type non-reciprocal circuit element and integrated circuit having multiple ground surface electrodes and co-planar electrical interface

The present invention provides a microwave and millimeter wave circuit apparatus having a reduced size and which can be produced easily, improving productivity. The microwave and millimeter wave circuit apparatus includes: a grounding conductive layer,grounded; a first dielectric layer,formed on this grounding conductive layer,; a signal line selectively formed on this first dielectric layer,; a second dielectric layer,covering at least a portion of the signal line,; a cavity,formed in this second dielectric layer,and extending to the signal line,; a monolithic microwave integrated circuit,arranged in the cavity,and connected to the signal line,; and an antenna connected to the signal line

Microwave and millimeter wave circuit apparatus

A semiconductor device comprising a first semiconductor layer, a second semiconductor layer on the first layer, a source electrode and a drain electrode both in contact with the first layer, and a hole or electron injection electrode and a gate electrode both formed on the second layer; wherein the second semiconductor is one that has an electron affinity smaller than the first semiconductor when holes are injected or has a sum of an electron affinity and a band gap greater than the first semiconductor when electrons are injected; and wherein the injection electrode and the gate electrode are placed between the source electrode and the drain electrode in this order. In such device, the current driving capability can easily be increased by controlling the injection amount of holes or electrons and the current modulation can easily be controlled by a small capacitance gate electrode; and so operation at an extra-high frequency and an extra-high speed becomes possible.

High speed semiconductor device and an optelectronic device

For improvement in a transit time of electrons, there is disclosed a heterojunction field effect transistor fabricated on a semi-insulating GaAs substrate, comprising a first layer overlying the semi-insulating substrate and formed of a high-purity GaAs, a second layer overlying the first layer and formed of an n-type AlGaAs which is smaller in electron affinity than the high-purity GaAs, a source region penetrating from the first layer into the second layer so as to be in contact with the active channel layer formed in the first layer and formed of an gallium-rich AlGaAs, a drain region, and a gate electrode formed on the second layer, an energy gap takes place between the source region and the first layer due to a lower edge of the conduction band thereof higher in energy level than that of the high-purity GaAs, thereby accelerating electrons supplied from the source region to the active channel layer.

Process of fabricating a heterojunction field effect transistor

A method of selective epitaxial growth includes a step of selectively forming an insulator film on a predetermined region of a semiconductor substrate and a step of evaporating a starting material containing a Group III element in vacuum in the presence of a Group V element to grow epitaxially a III-V compound semiconductor selectively on the semiconductor substrate under the condition where the partial pressure of the Group III element just above the semiconductor substrate is greater than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the semiconductor substrate and is smaller than the equilibrium vapor pressure of the Group III element contained in the III-V compound semiconductor existing on the insulator film. When InAs is grown epitaxially and selectively on a GaAs substrate, the GaAs substrate is kept at 500.degree. to 650.degree. C. and when GaAs is grown epitaxially and selectively on the GaAs substrate, the GaAs substrate is kept at 700.degree. to 775.degree. C.

Growing community of inventors

Tokyo, Japan

Keiichi Ohata