Kabushiki Kaisha Toshiba

Keiichi Matsushita

Keitaro Shigenaka

Katsuyoshi Fukuda

Kazutaka Takagi

Naotaka Tomita

Yo Sasaki

A semiconductor device includes a substrate, a semiconductor layer having a buffer layer, a spacer layer, and barrier layer sequentially stacked on the substrate, and first and second ohmic electrodes installed on an upper surface of the barrier layer in the substrate to be separated from each other. Each of the first and second ohmic electrodes includes a portion formed on the upper surface of the barrier layer and electrode portions filling a plurality of grooves penetrating from the upper surface of the barrier layer through the barrier layer and the spacer layer and reaching a region of a two-dimensional electron gas layer formed in a spacer-layer side of the buffer layer, the electrode portions being in contact with side walls of each of the plurality of the grooves, and the portion formed on the upper surface of the barrier layer and the electrode portions are integrally formed.

III-N device with extended source and drain

According to one embodiment, a semiconductor device includes a semiconductor element, a mounting member including Cu, and a bonding layer provided between the semiconductor element and the mounting member. The bonding layer includes a first region including Ti and Cu, and a second region provided between the first region and the mounting member, and including Sn and Cu. A first position along the first direction is positioned between the semiconductor element and a second position along the first direction. The first position is where the composition ratio of Ti in the first region is 0.1 times a maximum value of the composition ratio of Ti. The second position is where the composition ratio of Sn in the second region is 0.1 times a maximum value of the composition ratio of Sn. A distance between the first position and the second position is not less than 0.1 micrometers.

Semiconductor device and method for manufacturing the same

A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=x&#x3c;=1) placed on the nitride based compound semiconductor layer; a nitride based compound semiconductor layer placed on the aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=x&#x3c;=1) and doped with a second transition metal atom; an aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=y&#x3c;=1) placed on the nitride based compound semiconductor layer doped with the second transition metal atom; and a gate electrode, a source electrode, and a drain electrode which are placed on the aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=y&#x3c;=1).

Semiconductor device and fabrication method of the semiconductor device

A power amplifying device includes earth parts which are connected with via holes for grounding, source electrode earth conductors which connect the earth parts, source electrodes which are coupled to the source electrode earth conductors, an inner source electrode which is not in contact with the source electrode earth conductors, a drain electrode, a gate electrode and an air bridge which directly connects the inner source electrode and earth parts.

Power amplifying device and coupled power amplifying device

A semiconductor device includes a substrate; a nitride based compound semiconductor layer placed on the substrate; an active area which is placed on the nitride based compound semiconductor layer, and is composed of an aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=x&#x3c;=1); an isolation region which performs isolation of the active area mutually; a gate electrode, a source electrode, and a drain electrode which have been placed on the active area surrounded by the isolation region; and a trench region formed by etching for a part of the active area under the gate electrode. The semiconductor device is highly reliable, high performance and high power and a fabrication method for the same is also provided.

Semiconductor device and fabrication method for the same

A semiconductor device and a fabrication method of the semiconductor device, the semiconductor device including: a substrate; a nitride based compound semiconductor layer placed on the substrate and doped with a first transition metal atom; an aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=x&#x3c;=1) placed on the nitride based compound semiconductor layer; a nitride based compound semiconductor layer placed on the aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=x&#x3c;=1) and doped with a second transition metal atom; an aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=y&#x3c;=1) placed on the nitride based compound semiconductor layer doped with the second transition metal atom; and a gate electrode, a source electrode, and a drain electrode which are placed on the aluminum gallium nitride layer (AlGaN) (where 0.1&#x3c;=y&#x3c;=1). Accordingly, piezo charge is inactivated, leakage current and current collapse are reduced, high frequency characteristics can be improved by obtaining a high resistivity semiconductor layer, and stable high frequency performance can be obtained.

A semiconductor device, which can prevent an element breakdown by alleviating of electric field concentrations, and can also prevent reduction of gain, includes: a source electrode formed on a semiconductor layer; a drain electrode formed on the semiconductor layer; a gate electrode formed between the source electrode and the drain electrode; an insulating film formed on the semiconductor layer and the gate electrode; a field plate electrode formed on the insulating film; and a resistor for connecting the field plate electrode and the source electrode.

A substrate for forming a semiconductor layer includes a plurality of linear convexes or grooves on a surface of the substrate by crystal growth. The plurality of linear convexes or grooves are formed along a direction of a cleavage plane of the semiconductor layer.

Substrate for forming semiconductor layer including alignment marks

The hybrid type infrared detector includes a plurality of photodiodes constructed by p-n junctions made of compound semiconductor material on a silicon substrate, a signal processing portion formed on another substrate, and a connecting member for electrically connecting the plurality of photodiodes with the signal processing portion, and for injecting carriers generated by the photodiodes into the signal processing portion, and is characterized in that partitioning portions are formed along the cleavage plane of the compound semiconductor material.

Hybrid type infrared detector

A semiconductor photoelectric converting device and an imaging device using such semiconductor photoelectric converting devices are provided according to the present invention, the semiconductor photoelectric converting device including an electric charge transfer area provided in a surface portion of a semiconductor substrate and a light-receiving area formed of a piezoelectric material, electrically connected to the electric charge transfer area and provided in contact with the semiconductor substrate, in which electric charges generated by a piezoelectric effect produced by a strain resulting from heat evolved upon the falling of light onto the light-receiving area are conducted to the charge transfer area.

Growing community of inventors

Kawasaki, Japan

Keiichi Matsushita