Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Panasonic Intellectual Property Management Co., Ltd.

Keiichi Kusumoto

Akira Matsuzawa

Yutaka Terada

Hiroyuki Yamauchi

Hironori Akamatsu

Toru Iwata

Satoshi Takahashi

Takashi Hirata

Kenji Murata

Tetsurou Toubou

Shiro Dosho

Tsuguyasu Hatsuda

Toshiyuki Moriwaki

Kazuyuki Nakanishi

Takashi Yamada

Shozo Ochi

Takashi Ando

Kenji Shimazaki

Takashi Andoh

Kazuya Ushirokawa

Tomoyuki Kumamaru

Youichi Okamoto

Ken Yasue

Tetsuji Gotoh

An implementing structure intermediate body including: a first chip having a first connection terminal; a second chip having a second connection terminal in a face that faces the first chip; and a film wiring substrate having a third connection terminal in one face, which is arranged between the first chip and the second chip, is loaded on a chip loading substrate having a fifth connection terminal so that another one face of the first chip is confronted thereby. In the film wiring substrate, there is a portion that is located outside any of the first chip and the second chip, at the tip part, is provided a fourth connection terminal connected to the third connection terminal by wiring, one part of the first connection terminal is connected with the second connection terminal, the third connection terminal is connected with another one part of the first connection terminal, and the fifth connection terminal is connected to the fourth connection terminal.

Electronic component implementing structure intermediate body, electronic component implementing structure body and manufacturing method of electronic component implementing structure body

A semiconductor integrated circuit device includes cells A-1, B-1, and C-1 that have the same logic. Cell B-1 has cell width Wlarger than a cell width of cell A-1, but gate length Lof a MOS transistor is equal to that of cell A-1. Cell C-1 has cell width Wequal to a cell width of cell B-1, but has a MOS transistor having large gate length L. A circuit delay of cell C-1 becomes large as compared with that of cells A-1 and B-1, but leak current becomes small. Therefore, by replacing cell A-1 adjacent to a space area with cell B-1, and by replacing cell B-1 in a path having room in timing with cell C-1, for example, leak current can be suppressed without increasing a chip area.

Semiconductor integrated circuit device having a plurality of standard cells for leakage current suppression

In an integrated circuit device, element power supply lines connected to a circuit containing a plurality of cells, element ground lines connected thereto, a trunk power supply line connected to each of the element power supply lines, and a trunk ground line connected to each of the element ground lines are provided in a first wiring layer. A branch power supply line connected to the trunk power supply line and a branch ground line connected to the trunk ground line are provided in an upper wiring layer located above the first wiring layer. A wiring structure is determined based on a wiring structure equation expressing the relations among a voltage drop in the lines, the area occupied thereby, and a current consumed thereby and on a circuit characteristic equation expressing, when the circuit is subdivided while the ratio between the area of the circuit and a current consumed thereby is held constant, the relation between an area occupied by a circuit resulting from subdivision and a current consumed thereby.

Integrated circuit device and method for forming the same

A signal is transmitted in synchronization with a clock signal that repeats H and L levels indicating a preparation period and a transmission period, respectively. A transmitting circuit includes a transmitting capacitor, an input switch for setting a voltage in accordance with an input digital signal in the transmitting capacitor at preparation period, and a transmitting switch for generating a small voltage change in the signal line at transmission period, the voltage change being in accordance with a voltage of the transmitting capacitor. A receiving circuit includes an inverter with a CMOS configuration, a receiving capacitor inserted between an input terminal and an output terminal of the inverter, an equalizing switch for short-circuiting the input terminal and the output terminal of the inverter so as to set the voltage of the signal line to a predetermined voltage at preparation period, and a latch for supplying an output digital signal by performing logic amplification of the voltage of the output terminal of the inverter for each transmission period, and for holding the output for each preparation period.

Signal transmission circuit

The invention provides a semiconductor device that can inspect the connection states of power source terminals and grounding terminals of a test LSI at a low cost and in a short time, and an inspection method for the same. Switches SWto SWare provided between a plurality of power source terminals PDto PDand a power source lineinside the test LSI. A switch SWT is provided between the power source line and a grounding lineinside the test LSI. When inspecting the connection state of a certain power source terminal, the switch connected between the power source terminal and the power source line is closed, the switch SWT between the power source line and the grounding line is closed, and remaining switches are opened. A voltage is supplied between the power source terminal and a grounding terminal, and whether or not the power source terminal is in the connected state is determined by whether or not a current flows.

Semiconductor device having a connection inspecting circuit for inspecting connections of power source terminals and grounding terminals

Semiconductor device having a connection inspecting circuit for inspecting connections of power source terminals and grounding terminals, and inspection method for the same

In a static circuit or the like, upper and lower terminals are both set to a first power supply potential Vdd in the operating state of an inverter circuit. In the non-operating state, the power supply potential of the upper terminal is reduced to a second power supply potential Vdd (<<Vdd ). Provided that an input signal of the inverter circuit has a potential Vdd (H level), an output signal thereof must be held at the ground potential (L level) in the operating state. This requires that a conductance Gp of a PMOS transistor and a conductance Gn of a NMOS transistor satisfy the relation: Gp<Gn. Therefore, a well terminal (lower terminal) of the PMOS transistor is set to a potential higher than the power supply potential Vdd in order to maintain the relation: Gp<Gn. Accordingly, a signal determined by the circuit in the operating state can be held even in the non-operating state, and the power supply voltage is set to an extremely low potential in the non-operating state of the circuit.

Semiconductor integrated circuit for holding an output signal of an output terminal in a non-operating state

A power supply apparatus,comprises an energy supplying circuit,for supplying energy at a predetermined timing, and an energy preserving circuit,for receiving the energy supplied from the energy supplying circuit,and preserving the energy. The energy preserving circuit,includes an inductor,a capacitance,connected to one end of the inductor,at a node,and a capacitance,connected to the other end of the inductor,at a node,Energy is supplied to a load via at least one of the node,and the node

Power supply apparatus with energy return for reuse

The semiconductor device of this invention includes: an array section including a plurality of circuit blocks; a leakage current cutoff section for cutting off a leakage current occurring in at least one of the plurality of circuit blocks in the array section; and a control section for controlling the leakage current cutoff section in accordance with leakage current cutoff information.

Semiconductor device capable of cutting off a leakage current in a defective array section and method thereof

Growing community of inventors

Hyogo, Japan

Keiichi Kusumoto