Kabushiki Kaisha Toshiba

Keiichi Kushida

Osamu Hirabayashi

Nobuaki Otsuka

Yusuke Niki

Akira Katayama

Gou Fukano

A semiconductor memory device includes a memory cell, a pair of local bit lines connected to the memory cell, first and second transistors, one end of the current channel of each connected to a power supply and the other end of the current channel of each connected to one of the local bit lines, third and fourth transistors, one end of the current channel of each connected to one of the local bit lines, the other end of the current channel of each connected to one of the global bit lines, fifth and sixth transistors, one end of the current channel of each connected to one of the global bit lines and the other end of the current channel of which connected to the power supply. The device further includes a control unit configured to control the transistors.

Semiconductor memory device

According to one embodiment, there is provided a semiconductor memory device including a memory cell. The memory cell includes a first driving transistor, a first load transistor, a first read transfer transistor, a first write transfer transistor, a second driving transistor, a second load transistor, a second read transfer transistor, a second write transfer transistor, and one or more variable resistance elements. The one or more variable resistance elements has resistance that changes depending on a direction of a bias applied to both terminals. The one or more variable resistance elements are arranged in at least one of a portion between a first storage node and a first write transfer transistor and a portion between a second storage node and a second write transfer transistor.

According to the embodiments, a semiconductor storage device includes a memory cell array, a plurality of word lines, a plurality of bit lines, and a row selector that multiply-selects the word lines, wherein the semiconductor storage device satisfies N/N&#x2266;(4&#xd7;C&#xd7;V)/(I&#xd7;T),

Semiconductor storage device

A channel layer is deposited on a first impurity layer, a second impurity layer is deposited on the channel layer, a gate electrode is placed to surround a circumference of the channel layer with a gate insulating film interposed therebetween, a spin-injection magnetization-reversal element is deposited on the second impurity layer, a bit line is placed on the spin-injection magnetization-reversal element, and a word line is placed on the bit line to be electrically connected to the gate electrode.

Semiconductor memory device and manufacturing method for semiconductor memory device

The semiconductor memory device executes, in address units, operation for inverting data stored in a memory cell designated by an internal address and writing the data in the memory cell and increments the internal address every time inversion writing operation for the memory cell is executed.

Semiconductor memory device and method of updating data stored in the semiconductor memory device

In one embodiment, a semiconductor storage device includes a memory cell, a sense amplifier, a bit line, a pre-charge circuit, and a power-supply-voltage switching circuit. The memory cell is configured to store data. The sense amplifier is configured to amplify a signal from the memory cell. The bit line is configured to transmit the signal from the memory cell to the sense amplifier. The pre-charge circuit is configured to pre-charge the bit line. The power-supply-voltage switching circuit is configured to switch a voltage of a power supply and to actuate the sense amplifier after the bit line is pre-charged by the pre-charge circuit, wherein the power-supply-voltage switching circuit is configured to switch the voltage of the power supply to be larger than a voltage during the pre-charge by the pre-charge circuit.

Semiconductor storage device with bit line pre-charge circuit

An SRAM cell includes one pair of drive transistors, one pair of load transistors, one pair of write access transistors, one pair of read drive transistors, and one pair of access transistors. A voltage source potential is supplied to drains of the read drive transistors.

A semiconductor memory device includes a first write bit line, a second write bit line, a write word line, a first read bit line, a read word line, and a memory cell array including a plurality of memory cells, and arranged the plurality of memory cells in a matrix fashion, wherein the memory cells including a first inverter including a first PMOS transistor and a first NMOS transistor, a second inverter including a second PMOS transistor, and a second NMOS transistor, and including an input terminal and an output terminal connected to an output terminal and an input terminal of the first inverter, respectively, a first write transfer transistor connected between a first write bit line and the output terminal of the first inverter, and including a gate connected to a write word line, a second write transfer transistor connected between a second write bit line and the output terminal of the second inverter, and including a gate connected to the write word line, a first read driver transistor including a gate connected to the input terminal of any one of the first inverter and the second inverter, and a first read transfer transistor connected to a first read bit line through the first read driver transistor, and including a gate connected to a read word line, the first read transfer transistor shared by at least two of the memory cells in the memory cell array.

A semiconductor memory device comprises a word line; a bit line crossing the word line; a memory cell connected to intersection of the word line and the bit line; and a sense circuit connected to sense node coupled to the bit line. The sense circuit includes a first transistor of the first conduction type having a gate connected to the sense node, a second transistor of the second conduction type having a source connected to a first power supply, a drain connected to the sense node, and a gate connected to the drain of the first transistor, a third transistor having a source connected to the first power supply, a drain connected to the drain of the first transistor, and a gate connected to a control signal line, and a fourth transistor having a source connected to a second power supply, a drain connected to the source of the first transistor, and a gate connected to the control signal line. The sense circuit is activated with a control signal given to the control signal line.

Semiconductor memory device with sense circuit connected to sense node coupled to bit line

An integrated circuit device includes a plurality of memory circuits, a memory hibernation state control circuit to bring the memory circuits into a hibernation state in response to an external command, a state controller which indicates an interrupt in a memory circuit in a hibernation state, and a plurality of partial error checking and correcting (ECC) code generating circuits which are provided for the memory circuits, respectively, to code hold data of an address of a memory circuit in a hibernation state in accordance with a rule of a Hamming code determinant by an interrupt in the memory circuit in the hibernation state. The integrated circuit device further includes a code storage memory which obtains ECC code data corresponding to all of the hold data based on partial ECC codes coded by the partial ECC code generating circuit and stores the ECC code data in a corresponding address.

Integrated circuit device including a circuit to generate error correction code for correcting error bit for each of memory circuits

A semiconductor memory device comprises a plurality of cell arrays, each cell array containing a plurality of word lines, a plurality of bit lines crossing the word lines, and memory cells connected at intersections of the word lines and bit lines, the cell arrays arranged along the bit line; a plurality of bit line gates provided between the cell arrays and each operative to establish a connection between the bit lines in adjacent cell arrays; and a controlling circuit operative to form a data transfer path via the connection between the bit lines formed through the bit line gate when the controlling circuit accesses to the memory cell.

A semiconductor memory device includes a first block and a second block adjacent to each other in a column direction, each block including first and second memory cell arrays each including a plurality of local bit lines and a local sense amplifier shared by the first and second memory cell arrays, a plurality of global bit lines shared by the first block and the second block, a global sense amplifier configured to sense data transferred to the global bit lines, first and second replica cell groups provided in the first and second blocks, first and second replica bit lines connected to the first and second replica cell groups, an activation circuit connected to each replica bit line, and configured to activate the local sense amplifier, an edge cell group surrounding the first block and the second block, and a contact region surrounding the edge cell group.

Semiconductor memory device including a static memory cell

A semiconductor memory device includes a plurality of memory cell columns each having a plurality of memory cells, each memory cell including being a static type, a plurality of local bit lines connected to the memory cell columns, a global bit line connected to the local bit lines via a plurality of sense amplifiers, a measurement terminal to which a measurement voltage is applied in a cell current measurement mode, and a plurality of switching circuits provided to correspond to the local bit lines, and configured to electrically connect the measurement terminal and one of the local bit lines in the cell current measurement mode.

Semiconductor memory device having local and global bit lines

A programming method of a MOS electric fuse including preparing, as a fuse element, a MOS transistor which has a first impurity region and a second impurity region, both of a second conductivity type, formed to face with each other on an upper surface of a well of a first conductivity type on a semiconductor substrate, a gate dielectric film formed on the upper surface of the well at least between the first impurity region and the second impurity region, and a gate electrode formed through the gate dielectric film on the upper surface of the well held between the first impurity region and the second impurity region, and applying a first voltage to the gate electrode, and a second voltage different from the first voltage to the first impurity region, and short-circuiting the gate dielectric film only between the gate electrode and the first impurity region.

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Kawasaki, Japan

Keiichi Kushida