Kawasaki Steel Corporation

Keiichi Kawana

Masato Yoneda

Norimitsu Sako

Masahiro Konishi

An associative memory device is cascade-connected to form an associative memory. The associative memory device includes a retrieval result register for storing a retrieval result of the lo associative memory device and the retrieval result of the associative memory devices of an upstream side of the associative memory device. An identification code register stores an identification code that indicates whether the associative memory device is a last stage associative memory device of the cascade-connected associative memory devices. If the associative memory device is the last stage associative memory device, the retrieval result stored in the retrieval result register is output. The associative memory outputs the retrieval result only when a signal instructing an output of the retrieval result is received.

Associative memory

A semiconductor integrated circuit capable of electrically writing functions according to this invention comprises a plurality of logical blocks capable of electrically writing functions and wire elements capable of programmably connecting the logical blocks to each other. Each of the logical blocks includes a gate element as an output buffer having a control terminal. The gate element assumes a high impedance state when inputting a control signal to the control terminal. An output of the logical block is thereby made unable; or the respective logical blocks are directly wired-connectable to effect logical sum outputting. Alternatively, the gate element assumes two output states of an open drain output and a totem-pole output. Hence, in the semiconductor integrated circuit of this invention, it is possible to improve a gate using efficiency of the small-sized programmable logical blocks and attain a high-density and high-integrated programmable logic device.

Programmable logic device

A programmable logic device of the present invention is constructed to reduce the number of switching elements in wire switches when programmably connecting logical elements by using wire groups. A plurality of programmable wire groups are wired in vertical and horizontal channels between logical elements arranged in array. The wire groups are combined to intersect preferably in crosses. The wire groups are short-circuit-connected at the intersections or connected through programmable switching elements. Programmable connections are effected through wire switching means middled between the wire elements provided between the adjacent intersections. Hence, the programmable logic device of this invention is capable of reducing the areas occupied by the switching elements in the switching means and attaining a high degree of freedom of wiring and a high integration.

A programmable integrated circuit of the present invention can change the input system of serial/parallel input-parallel output circuit for program data from serial to parallel or vice versa in response to a control signal from control signal input. Therefore, a program can be written at a relatively low speed through the parallel output of serial input, and a program can be written at a relatively high speed by inputting data in parallel and outputting the input data in parallel. Moreover, the bit width of the aforementioned serial/parallel input-parallel output circuit can be changed in response to a control signal from control signal input, whereby bit width for data input, shift and the like can be optimized according to the quantity of programs to be written with the result of improved freedom of users and the reduced time required for writing a large quantity of programs.

Programmable integrated circuit

There are provided, in addition to an ordinary operation word line for controlling a non-volatile memory upon regularly writing or reading information, a testing word line, a selection transistor, and a storage capacitor, whereby an input signal is transferred onto the testing word line upon inspection to switch on the selection transistor and hence the information is transferred into the capacitor through a bit line for writing into and reading from the capacitor. More specifically, the selection transistor and the capacitor are operated as in a DRAM to diagnose the function of an integrated circuit chip without operation of the non-volatile memory.

Integrated circuit including non-volatile memory cell capable of

In a programmable input/output circuit which is used in a programmable integrated circuit, for interfacing between an external circuit and an internal logic circuit, both disposed exteriorly and interiorly of said integrated circuit, an input/output terminal connected to a bus of the internal logic circuit and a tri-state input buffer are provided, and hereby assured that an external input signal is transmitted to either of the input/output terminal and an ordinary input terminal by switching the status of the tri-state input buffer. In a programmable logic device, which incorporates said input/output circuit, a tri-state buffer is provided between an input/output circuit block and a wiring element, and hereby a driving capability of the wiring element used as a bus line is increased.

Programmable input/output circuit and programmable logic device

In a programmable input/output circuit connected to an input terminal or an output terminal of an integrated circuit, a desirable combination from signals including a signal of the input terminal, an input or output signal of a storage element, an input or output signal of a combinational logic circuit, an input or output signal of another selector and the like is selected by use of at least one programmable selector, processed and output into the output terminal, so that an input or output circuit for performing a desirable signal process can be provided. Further, at least one dynamic selector circuit is provided, so that an output signal from another input/output circuit can be input into the storage element and an output signal from the storage element can be supplied to another input/output circuit.

Growing community of inventors

Chiba, Japan

Keiichi Kawana