Ricoh Company, Ltd.

Sony Corporation

Keiichi Iwasaki

Kazuyuki Shimada

Takahiro Yagishita

Toshihiro Tsukagoshi

Masayoshi Miyamoto

Yoshiharu Niito

Hideo Azumai

Tomonori Tanaka

Noriyuki Terao

Junichi Ikeda

Hiroo Kitagawa

Hidetake Tanaka

Iwao Hamaguchi

Satoru Numakura

Naoki Tsumura

Hiroyuki Kimbara

Koji Oshikiri

Yukitoshi Kiya

Yutaka Maita

Atsuhiro Oizumi

Kiyoshi Nakagawa

Yukimasa Yamaguchi

Yikitoshi Kiya

A spread spectrum clock generator includes a phase comparator that compares a reference clock with a feedback clock, a low-pass filter that passes a predetermined low-frequency component, a phase lock loop that includes a voltage-controlled oscillator generating an output clock whose frequency corresponds to the filtered signal, a triangular wave controller that generates a triangular wave signal for frequency-modulating the spread spectrum clock based on the output clock, a delay controller that generates the feedback clock by controlling delay of the output clock based on the triangular wave signal, a first counter that counts the output clock and output a first count value, a second counter that counts the reference clock and output a second count value, and a phase error correction circuit that compares the first count value with the second count value and corrects phase error of the output clock.

Spread spectrum clock generator, electronic apparatus, and spread spectrum clock generation method

A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.

Memory control device and a delay controller

A disclosed synchronous memory control apparatus for enabling reception of data read from a memory circuit in synchronism with a strobe signal from the memory circuit includes a mask circuit masking the strobe signal using a mask signal; a timing measuring circuit delaying the strobe signal in plural units of delay and latching data of each of the delayed strobe signals; and a mask generating circuit generating the mask signal. The timing measuring circuit latches the data of each of the delayed strobe signals at the first rise edge of the corresponding masked strobe signal. The mask generating circuit includes a delay circuit having plural units of delay. A start timing of the mask signal is adjusted in synchronism with an internal clock, and a signal having a delay amount corresponding to a selected unit of delay by the delay circuit is outputted as the mask signal.

Memory control apparatus and mask timing adjusting method

An image pickup apparatus includes a housing, a lens incorporated in the front of the housing and configured to constitute an imaging optical system, an image pickup device provided in the housing and configured to capture a subject image guided by the imaging optical system, a printed wiring board provided in the housing and having the image pickup device mounted thereon, a barrel provided integrally with the front of the housing, an annular lens cover configured to push a face of the lens facing forward in a rearward direction, and detachably mounted on the front of the barrel, and a support wall projecting rearward outside a rear end of the barrel in the radial direction and inside the housing, and bonded to the printed wiring board with adhesive.

Image pickup apparatus

An information processor that is connected to at least one other information processor via a network, includes a detecting unit that detects an optional device to be used for information processing, as a target optional device, installed on the other information processor, an issuing unit that issues an access request to use the target optional device to the other information processor, a receiving unit that receives an access permission for access to the target optional device from the other information processor, and a processing unit that performs the information processing with the target optional device.

Information processor configured to detect available space in a storage in another information processor

First to fourth lenses are aligned in an optical axis direction by a lens-barrel of a camera, an O-ring is disposed between the first lens and the lens-barrel, an O-ring is disposed between the fourth lens and the lens-barrel, a space is formed between the first and second lenses, a space is formed between the second and fourth lenses, a space is formed between the third and fourth lenses, and flow of air between the spaces is precluded. The camera thus configured is free of dewing on the lens or a protective plate exposed to the exterior, even when the inside temperature is raised due to heat generation in a CCD or a mounting substrate on which the CCD is mounted.

Camera

A high-speed serial switch fabric is configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel. The high-speed serial switch fabric connects a plurality of devices. A traffic-class setting unit sets, when a conflict occurs between devices connected to the high-speed serial switch fabric, the traffic class for each of traffics in the devices having the conflict. A channel setting unit assigns each of set traffic classes to different virtual channels, and gives a priority of data communication to each of the set traffic classes.

High speed serial switch fabric performing mapping of traffic classes onto virtual channels

A memory control device is disclosed that comprises a clock generator that generates a reference clock, a DLL circuit that receives the reference clock from the clock generator and outputs an output value indicative of a clock cycle of the reference clock, a delay setting circuit that receives the output value from the DLL circuit and outputs a delay setting value based on the output value according to at least one parameter, and plural delay elements that receive the delay setting value and introduce a delay responsive to the delay setting value. One or more of the delay elements receive input signals from corresponding one or more flip-flops driven by drive clocks generated by the clock generator, and send output signals to corresponding one or more output buffers that are to be connected to a memory.

Memory control device

A delay control apparatus includes first and second delay elements each configured to receive and delay a strobe signal and clock by a prescribed delay value. A prescribed number of flip-flops is provided to input data upon receiving the strobe signal output from the second delay element. The second delay element delays and outputs the strobe signal by the prescribed delay value to the flip-flops when the selection device selects the strobe signal. A phase comparator compares clocks output from the first and second delay elements. A delay control device changes the prescribed delay value of the second delay element in accordance with the comparison result of the phase comparator when the selection device selects the clock.

Jitter and skew suppressing delay control apparatus

A character table unit stores as attribute data of each character of an image a character name, a horizontal direction character size, a vertical direction character size, a horizontal display coordinate value and, a vertical display coordinate. A counter outputs count values indicating a horizontal position and a vertical position in a display screen image. A first writing control unit reads from the character table unit the attribute data of an appropriate character based on the count values of the counter and the attribute data, produces basic size attribute data of basic size characters which constitute at least part of the character. The basic size character is determined to be currently displayed based on the count values. The basic size character attribute data is written in a hit buffer. A image data memory stores character image data. A second writing control unit reads basic size attribute data from the hit buffer, producing addresses based on the basic size attribute data to read character image data from the image data memory, and writing the character image data into a line buffer. Image data is read from the line buffer, in synchronization with the count value indicating a current horizontal position.

Image display control device, method and computer program product

A VRAM stores a plurality of patterns of image data, an offset register stores values which indicate definition starting positions from which display image data are defined from the plurality of patterns of image data, respectively, a horizontal counter counts dots in a horizontal scanning direction, and a vertical counter counts lines in vertical scanning direction. Address and control signals are successively provided for reading a respective line of the display image data from the VRAM within one horizontal scanning period, based on the values of the offset register and the value of the vertical counter. Each of two second storage devices has a storage capacity for storing a thus-read respective line of the image data. Thus-read image data is written at addresses of a predetermined one of the two second storage devices, the addresses corresponding to displaying dots of the image data, while, according to the value of the horizontal counter, image data stored in the other one of the two second storage devices is read out, where, the image data writing and reading operations are performed alternately between the two second storage devices for each horizontal scanning period.

A phase-locked loop with memory storing control data. The control data to be given to a voltage-controlled oscillator in a phase-locked loop is addressed in accordance with an oscillation condition including the frequency of a reference signal, a dividing ratio of the frequency divider and ambient air temperature. When the phase-locked loop is controlled off, the control voltage for the voltage-controlled oscillator is changed into digital data by an analog-to-digital converter to be transferred to the memory. The digital data or control data is read out from the memory when the phase-locked loop is controlled on. The control data is then changed into analog equivalent as control voltage supplied to the voltage-controlled oscillator, shortening the locking-up time.

Phase-locked loop with memory storing control data controlling the

An image forming apparatus includes an image forming part for forming an image described by a video signal on a recording sheet by carrying out an image forming operation which includes scans in main and sub scan directions, a storage part for storing test pattern data which describes at least one test pattern to be formed on the recording sheet, a generator for generating a generation interval of the video signal in the main and sub scan directions responsive to the test pattern data stored in the storage part, and a controller for controlling the image forming operation of the image forming part by supplying to the image forming part the video signal which describes an arbitrary test pattern and is generated based on the test pattern data read from the storage part with the generation interval generated by the generator.

Image forming apparatus

An image recording apparatus includes an image recording media, an optical scanning system selected from among predetermined different optical scanning systems, a first memory for storing a plurality of sets of control data respectively provided for the different optical scanning systems, a switch for specifying one of the predetermined different optical scanning systems provided in the image recording apparatus, and a second memory for storing one of the sets of control data corresponding to the optical scanning system selected from among the predetermined different optical scanning systems. Also, the apparatus includes a main scan controller which generates predetermined timing signals related to the one of the sets of control data stored in the second memory, and a control part for generating a control signal from the one of the sets of control data and the predetermined timing signals and for controlling the optical scanning system on the basis of the control signal so that the optical scanning system actually provided in the image recording apparatus has an optical characteristic based on the one of the sets of control data related to the optical scanning system actually provided in the image recording apparatus.

Recording apparatus having control data selectively designated in memory

An image forming apparatus includes a photosensitive drum, a laser diode, and an optical scanning system provided between said laser diode and the photosensitive drum, for scanning the recording medium by deflecting the light beam emitted from the laser diode to thereby form an image on the recording medium. The optical scanning system has one of predetermined optical characteristics different from each other. The apparatus further includes a memory which stores a plurality of sets of control data provided for the predetermined optical characteristics of the optical scanning system. The control data is used for controlling the laser diode. Further, the apparatus includes a control data selecting circuit which selects one of the sets of control data which relates to the one of the predetermined optical characteristics of the optical scanning system, and a controller for controlling the laser diode on the basis of image data and the selected one of the sets of control data.

Growing community of inventors

Kanagawa, Japan

Keiichi Iwasaki