Synaptics Japan Gk

Renesas Sp Drivers Inc.

Keiichi Itoigawa

Takashi Tamura

Jun Kurosawa

Yoshihiko Hori

Takefumi Seno

Kazuhiko Kanda

Hideaki Kuwada

Tomoo Minaki

Tomomitsu Kitamura

Shinichi Ogou

A semiconductor device includes first and second buffers respectively outputting reception data and clock signals; a latch circuit latching the reception data signal in response to the reception clock signal; a delay circuitry delaying the reception clock signal by a set delay time; and a delay control circuitry which searches a first delay time while increasing the set delay time from an initial value; searches a second delay time while increasing the set delay time from the first delay time; searches a third delay time while decreasing the set delay time from the second delay time; and determines an optimum delay time from the first and third delay times. The first and third delay times are determined so that the reception data is stabilized to a first value and the second delay time is determined so that the reception data is stabilized to a second value.

Device and method for skew compensation between data signal and clock signal

A semiconductor device includes first to sixth external connection terminals, a first receiver connected to the first and second external connection terminals, a second receiver connected to the third and fourth external connection terminals, a third receiver connected to the fifth and sixth external connection terminals, a C-PHY block, a D-PHY block and a main processing section. The C-PHY block is configured to generate first reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI C-PHY specification. The D-PHY block is configured to generate second reception data by performing signal processing on signals received from the first, second and third receivers in accordance with the MIPI D-PHY specification. The main processing section is configured to selectively receive the first and second reception data and perform desired processing on the received data.

Semiconductor device and module adapted to both MIPI C-PHY and MIPI D-PHY

A receiver is composed of a receiver-side amplifier which receives a clock signal, a receiver-side amplifier which receives a data signal, a variable delay circuit which generates a delay-adjusted clock signal and a delay-adjusted data signal by delaying the clock signal and the data signal, a latch circuit section which latches the delay-adjusted data signal in synchronous with the delay-adjusted clock signal, and a skew detecting circuit which generates skew detection data that by latching a specific data sequence transmitted as the data signal in synchronous with a first clock signal to Nclock signal (N is an integer equal to or more than 2) with different delay times from the clock signal. The delay time in the variable delay circuit is controlled according to the skew detection data.

Receiver and transmission and reception system

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Tokyo, Japan

Keiichi Itoigawa