Hitachi, Ltd.

Other

Renesas Technology Corp.

Hitachi Ulsi Systems Co., Ltd.

Hitachi Device Engineering Co., Ltd.

Keiichi Higeta

Shigeru Nakahara

Takeshi Suzuki

Hiroaki Nambu

Kazuo Kanetani

Kunihiko Yamaguchi

Takeshi Kusunoki

Akihisa Uchida

Kaname Yamasaki

Fumihiko Arakawa

Satoshi Iwahashi

Hideki Hayashi

Takashi Koba

Katsumi Ogiue

Satoru Isomura

Masahiko Nishiyama

Yasuhiro Fujimura

Ichiro Mitamura

Atsushi Shimizu

Tohru Kobayashi

Yuko Ito

Takahiro Kawata

Takeo Yamada

Kengo Miyazawa

Takeo Shiba

Noriyuki Sakuma

Kazutaka Mori

Masanori Odaka

Mitsugu Kusunoki

Kiichiro Mukai

Masato Hamamoto

Nobuo Tamba

Takayuki Muranaka

Kenichi Ohhata

Atsushi Wakahara

Isao Kimura

Kazuhiro Akimoto

Takashi Muto

Junji Baba

Yasushiro Nishioka

Hiroshi Shinriki

Hideyuki Takahashi

Sohei Omori

Toru Koizumi

Naoyuki Anan

Yoichiro Aihara

Masaki Kouno

Takao Saotome

Mikiko Sakai

Seryung Park

Etsuko Iwamoto

Etsuko Kawaguchi

Hiroyuki Tanaka

In a data transfer device which cancells an offset of a differential amplifier for amplifying a received signal and an offset caused by characteristics of a differential transmission line and selects optimum conditions such as pre-emphasis amount of an output pre-emphasis circuit, a first chip (transmission side LSI=transfer engine) and a second chip (reception side LSI=multiplexing engine) are connected to each other through differential transmission lineand a SerDes (serializer)and a SerDes (deserializer)are used to make signal transmission, so that optimum setting conditions of an offset amount of an offset cancellation circuit included in an input buffer amplifier and a pre-emphasis amount of pre-emphasis circuit included in an output buffer are decided in training using a training PRBS generatorand a training PRBS comparator

Data transfer device of serializer/deserializer system

A circuit system is provided capable of improving the throughput thereof by eliminating the operational constraint that if the operating frequency of a content addressable memory is lower than the operating frequency of a system LSI, two system clocks should be provided, or the higher frequency should be synchronized with the slower system clock. A clock control circuit () for down-converting an internal clock (&#x3a6;) of a LSI () is provided, and a control signal whose frequency is made lower is used to operate a content addressable memory circuit ().

Semiconductor integrated circuit and image processing system using the same

There is provided a control circuit () for fetching a result of a comparison of a part of bits of entry data with a corresponding bit of comparison data and prohibiting a comparison of residual bits in the entry data with the corresponding bit of the comparison data when the result of the comparison is mismatched, and the comparison of the residual bits in the entry data with the corresponding bit of the comparison data is prohibited. Consequently, the number of signal lines to be activated in one cycle of a comparing operation is decreased. Thus, a reduction in a consumed power can be achieved.

Semiconductor memory device

The present invention provides a novel semiconductor integrated circuit device equipped with memory circuits, high-speed memories and large memory capacity memory circuits, which enables speeding up and facilitation of timing settings. The semiconductor integrated circuit device is provided with first amplifier circuits; which include first MOSFETs of first conductivity type, which have gates provided for a plurality of bit lines to which memory cells are respectively connected, and which are respectively maintained in an off state under precharge voltages supplied to the bit lines, as read circuits of the memory cells determined as to whether memory currents flow according to the operation of selecting word lines and memory information; and which are respectively brought to operating states in association with select signals for the bit lines, and also provided with a second amplifier circuit including; a plurality of second MOSFETs of second conductivity type, which have gates respectively supplied with a plurality of amplified signals of the first amplifier circuits and which are connected in parallel configurations; and which forms an amplified signal corresponding to the amplified signals of the first amplifier circuits.

Semiconductor integrated circuit device

To reduce the width of isolation between the first and second p channel MIS&#x2022;FETs driven by different voltages, a first p channel MIS&#x2022;FET driven by a first supply voltage and a second p channel MIS&#x2022;FET driven by a second supply voltage higher than the first supply voltage are arranged in the same n well of the same semiconductor substrate, and the second supply voltage is supplied as a common well bias voltage to the n well.

Semiconductor device

Data lines (D, D) are shared by a first storage portion (MA) and a second storage portion (MB), and furthermore, a first transistor (MC) coupled to a first comparison data portion (CD) and a second transistor (MCA) coupled to the storage node of a first storage portion are connected in series to form a first comparing circuit (), and a third transistor (MC) coupled to a second comparison data line (CD) and a fourth transistor (MCB) coupled to the storage node of the second storage portion are connected in series to form a second comparing circuit (). Consequently, it is possible to enhance a symmetry in the layout of a diffusion layer and a wiring layer and to achieve the easiness of a layout in which a memory cell is line symmetrical with respect to a center line passing through a center thereof. Thus, a manufacturing process condition can easily be optimized and a variation in a manufacturing process can be reduced so that the microfabrication of the memory cell can be achieved.

To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit

A semiconductor integrated circuit device endowed with memory circuits achieving high operation margin and low energy consumption with high speed and high integration. Composing a memory cell with a MOSFET having a first threshold voltage corresponding to a first voltage and supplying a selection signal corresponding to said first voltage to a word line by a word driver driven at said first voltage. Corresponding to a second voltage smaller than said first voltage, forming a selection signal sending to said word driver by a decoder comprising MOSFET with a second threshold voltage smaller than said first voltage, operating at said first voltage, and installing a first level shifting circuit including inverter circuits that form a selection signal corresponding to said first voltage by receiving a selection signal corresponding to said second voltage. Thereby, high operation margin and low energy consumption with high speed and high integration can be achieved.

A semiconductor memory device having a memory array comprising CMOS flip-flop circuit type memory cells, which is capable of improving a noise margin, making a read rate fast and reducing power consumption. In the semiconductor memory device, an operating voltage of the memory cell is set higher than an operating voltage of each of peripheral circuits. Threshold voltages of MOS transistors that constitute the memory cell, are set higher than those of MOS transistors constituting the peripheral circuit. A gate insulting film for the MOS transistors that constitute the memory cell, is formed so as to be regarded as thicker than a gate insulting film for the MOS transistors constituting the peripheral circuit when converted to an insulating film of the same material. Further, a word-line selection level and a bit-line precharge level are set identical to the level of the operating voltage of the peripheral circuit.

A semiconductor memory device comprises a memory-cell array for storing data, a peripheral circuit for carrying out an operation to read out or write data from or into the memory-cell array, read clock generation circuits (and) each used for generating a read clock signal to be supplied to the peripheral circuit in the operation to read out data from the memory-cell array, write clock generation circuits (and) each used for generating a write clock signal to be supplied to the peripheral circuit in the operation to write data into the memory-cell array. Since the pulse widths of the clock signals in read and writes are adjusted individually, margin insufficiencies of the pulse widths can be evaluated and results of the evaluation can be fed back to a design phase for, among other purposes, correction of a layout.

The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.

Semiconductor integrated circuit device with a RAM macro having two operation modes for receiving an input signal at different timings

In a dynamic-type semiconductor integrated circuit in which precharge and evaluation operations are preformed per cycle, an IDDQ test and a light detection test can be conducted during an evaluation period for facilitating diagnosis and failure analysis so as to increase test accuracy. The dynamic-type semiconductor integrated circuit operates in a normal operation mode or a test mode, wherein a switch therebetween is triggered by a mode selection signal. In the normal operation mode, the pulse width of an internal activation signal is controlled to be constant, i.e., invariable with an operation cycle time length. In the test mode, the pulse width of the internal activation signal is controlled to vary according to an operation cycle time length.

Method of testing a semiconductor integrated device

Growing community of inventors

Hamura, Japan

Keiichi Higeta