Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Keiichi Higashitani

Motoshige Igarashi

Keiichi Yamada

Hiroshi Kawashima

Kenji Yoshiyama

Hiroyuki Amishiro

Masakazu Okada

Masao Sugiyama

Katsuya Okada

Masatoshi Kimura

Atsushi Maeda

Hiroyuki Chibahara

Takio Ohno

Hideyo Haruhana

Akihiko Harada

A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection filmis formed on a side of one gate electrode

Semiconductor device including multiple field effect transistors, with first FETs having oxide spacers and the second FETs having oxide nitride oxidation protection

A thermal process for activating respective impurities in a polysilicon film to be a gate electrode and a resistance element is performed with the polysilicon film to be the gate electrode and the resistance element being coated with an oxide film, after the respective impurities are implanted into the polysilicon film to be the gate electrode and the resistance element. Here, concentrations of the respective impurities in the polysilicon film to be the gate electrode and the resistance element are adjusted by controlling the thickness of the oxide film. The degree of impurity activation is thereby adjusted.

Method of manufacturing semiconductor device

There is described a method of manufacturing a semiconductor device of dual-gate construction, which method prevents occurrence of a highly-resistant local area in a gate electrode of dual-gate construction. A polysilicon layer which is to become a conductive layer of a gate electrode of dual-gate construction is formed on an isolation oxide film. N-type impurities are implanted into an n-type implantation region of the polysilicon film while a photoresist film is taken as a mask. P-type impurities are implanted into a p-type impurity region of the polysilicon film 3 while another photoresist film is taken as a mask. Implantation of n-type impurities and implantation of p-type impurities are performed such that an overlapping area to be doped with these impurities in an overlapping manner is inevitably formed.

METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE OF DUAL-GATE CONSTRUCTION, AND SEMICONDUCTOR DEVICE MANUFACTURED THEREBY INCLUDING FORMING A REGION OF OVER-LAPPING N-TYPE AND P-TYPE IMPURITIES WITH LOWER RESISTANCE

A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film is formed on a side of one gate electrode

Semiconductor device including multiple field effect transistors and manufacturing method thereof

A silicon semiconductor substrate has a plurality of active regions having an impurity region and an isolating region which electrically isolates these active regions from each other. The isolating region is formed of a silicon nitride film. A contact hole penetrates an interlayer insulating film and reaches an impurity region. In this semiconductor device, when the contact hole falls across the impurity region and the isolating region, an amount of erosion in the isolating region is reduced.

Semiconductor device having an improved interlayer contact and manufacturing method thereof

A semiconductor device more reduced in size and a manufacturing method thereof are provided. A gate electrode is covered with a silicon nitride film having a selecting ratio greater than an NSG film under a prescribed etching condition. A cobalt suicide film is formed on an upper surface of source/drain regions. Furthermore, a refractory metal silicide film forming the gate electrode is formed by a cobalt silicide film.

Semiconductor device with self-aligned contact structure

Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of salicide structure are provided together, and a method of manufacturing the same. Each gate electrode ( ) of gate structures (GT to GT ) is covered with an upper nitride film ( ) and sidewall nitride film ( ). Therefore, when an interlayer insulating film ( ) being oxide film is selectively removed for forming contact holes (CH and CH ), the upper nitride film ( ) and sidewall nitride film ( ) are not removed, thereby preventing the gate electrode ( ) from being exposed. Particularly, in the gate structures (GT and GT ), even when the contact hole (CH ) is dislocated to either side, no short-circuit is developed between a conductor layer (CL ) and the gate electrode ( ). Thus, the gate structures (GT and GT ) can be disposed without being restricted by the alignment margin of the contact hole (CH ), and the distance between the gates can be reduced for attaining high integration.

Method for forming a semiconductor device having a plurality of circuits parts

There is described a method of manufacturing a semiconductor device which ensures formation of a step in an alignment mark, to thereby improve the accuracy of alignment. A tungsten layer is formed on an interlayer dielectric film including an opening for use in forming an alignment mark. The tungsten layer is abraded by means of the CMP technique. At this time, the initial thickness of the interlayer dielectric film is made greater than the total sum of the minimum step identifiable for alignment and the amount of abrasion, thus ensuring formation of an alignment step. Further, a gate electrode is removed from the position where a contact alignment mark is formed. Alternatively, an aluminum electrode is removed from a position immediately below a through hole alignment mark.

Method of manufacturing a semiconductor device, and a semiconductor device manufactured thereby

Provided are a semiconductor device in which a MOS transistor of SAC structure and a MOS transistor of silicide structure are are provided together, and a method of manufacturing the same. Each gate electrode (,) of gate structures (GT,to GT,) is covered with an upper nitride film (,) and sidewall nitride film (,). Therefore, when an interlayer insulating film (,) being oxide film is selectively removed for forming contact holes (CH,and CH,), the upper nitride film (,) and sidewall nitride film (,) are not removed, thereby preventing the gate electrode (,) from being exposed. Particularly, in the gate structures (GT,and GT,), even when the contact hole (CH,) is dislocated to either side, no short-circuit is developed between a conductor layer (CL,) and the gate electrode (,). Thus, the gate structures (GT,and GT,) can be disposed without being restricted by the alignment margin of the contact hole (CH,), and the distance between the gates can be reduced for attaining high integration.

Semiconductor device with electrical isolation means

A semiconductor device is implemented having dummy patterns arranged by designedly determining the ratio of area occupied by a protruded portion of an element formation region considering the deposited state of a buried insulating film which becomes an isolation insulating film. The ratio of area occupied by a protruded portion of a dummy pattern to a predetermined cell region is defined to be almost the same as the maximum or average value of ratios of areas occupied respectively by protruded element formation regions to a plurality of predetermined regions each including a plurality of predetermined cell regions.

Semiconductor device

There is described a semiconductor device which includes in a single chip a high withstanding voltage transistor and a low withstanding voltage transistor and which imparts each of the transistors with a relevant threshold voltage and a characteristic suitable for retarding hot carriers. Specifically, an impurity profile is imparted to a lightly-doped extension (LDDEX) region formed across a channel region of a low withstanding voltage NMOS transistor, and a different impurity profile is imparted to an LDDEX region formed across a channel region of a high withstanding voltage NMOS transistor. These impurity profiles bring the threshold voltages of the MOS transistors to individual relevant voltages and retard hot carriers in the individual MOS transistors.

Semiconductor device, and method for manufacturing the same

Semiconductor device provided with a field-effect transistor and method of manufacturing the same

A method of manufacturing a semiconductor device which prevents a short circuit between a gate electrode and a diffusion layer region if a contact hole is shifted from its proper position. A material having an etch selectivity to an interlayer insulation film is formed over the gate electrode to serve as a cover against the formation of a contact hole. A material is not formed over an interconnect line which is required to be exposed to a contact hole.

In a semiconductor device and a method of manufacturing the same, a dummy region which can suppress occurrence of a parasitic capacity can be provided for reducing a difference in level without increasing manufacturing steps in number. A semiconductor substrate is provided at its main surface with an isolation region formed by a trench, and a dummy region leaving the main surface is formed in the isolation region for the purpose of reducing an influence by the difference in level in a later step. The dummy region includes p- and n-type impurity regions each extending a predetermined depth from the surface. Since a pn junction occurs at the bottom of the impurity region, a depletion layer spreads in the pn junction, and thereby reduces a parasitic capacity between the dummy region and a conductive interconnection located in a crossing direction at a higher position. The impurity regions and source/drain regions of p- and n-channel transistors in active regions are simultaneously formed by impurity implantation.

Semiconductor device with improved planarity and reduced parasitic

A semiconductor device having a multi-level interconnection structure is disclosed which includes a metal interconnect wire (2) formed on a surface of an interlayer dielectric film (7) serving as a base; a high-stress TEOS oxide film (5), an SOG film (3), and a low-stress TEOS oxide film (6) which are deposited as interlayer dielectric films; and a contact hole (4), thereby decreasing stresses applied from the interlayer dielectric films to the metal interconnect wire to prevent metal hillocks in the contact hole.

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Hyogo, Japan

Keiichi Higashitani