Kabushiki Kaisha Toshiba

Keiichi Handa

Satoshi Ito

Toshibumi Seki

Akihiko Ohsuga

Yasuyuki Tahara

Yasuo Nagai

Shinichi Honiden

Nobuyuki Sawashima

Naoshi Uchihira

Hideaki Shiotani

Kazuhito Haruki

Takufumi Yoshida

Shigeta Kuninobu

According to one embodiment, an information processing apparatus includes processing circuitry. The processing circuitry is configured to combine a sell condition under which a first dealer sells a product and a buy condition under which a second dealer buys the product on a basis of information of a first transport medium to transport the product, and generate matching information including the sell condition and the buy condition combined each other; and assign a transport of the product to the first transport medium by associating the transport with the first transport medium and perform scheduling of the transport on a basis of the matching information.

Information processing apparatus, information processing method, and non-transitory computer readable medium

An apparatus for supporting parallelization according to the invention is characterized by comprising a serialization unit for converting a first concurrent program having a concurrent structure into a sequential program capable of being sequentially executed, a debugging unit for debugging the sequential program and forming debugging information, and a concurrent program programming unit for performing parallelization of the debugged sequential program on the basis of the debugging information to convert the sequential program into a second concurrent program. With above configuration, the debugging unit includes a unit for introducing information associated with concurrency to the sequential program.

Programming method for concurrent programs and program supporting apparatus thereof

A fault repair method including the steps of providing second memory cells as spare lines for repairing faulty elements of first memory cells for storing data therein, setting virtual third memory cells with respect to a repair target including said first memory cells and the second memory cells, and repairing the faulty elements of the first memory cells and the second memory cells by using the virtual third cells.

Method and device for repairing arrays with redundancy

Programming method for concurrent programs and program supporting

An LSI element placement method of placing elements in accordance with an order in which branches are arranged, each branch being constituted by an element array included in a circuit diagram having first and second terminals, the method including a partial circuit extraction step of sequentially extracting data of a predetermined number of branches included in the circuit diagram from the first terminal side of the circuit diagram so as to overlap the data by a predetermined number, and an element placement step of performing an element placement operation based on a genetic algorithm in the extracted partial circuit data, thereby generating an element placement result including placement coordinate data of all elements included in the partial circuit data.

Element placement method and apparatus

Growing community of inventors

Tokyo, Japan

Keiichi Handa