Taiwan Semiconductor Manufacturing Comp. Ltd.

National Cheng-Kung University

Other

Kei-Wei Chen

Ying-Lang Wang

Liang-Guang Chen

Chih Hung Chen

Hui-Chi Huang

Kuo-Hsiu Wei

Chun Hsiung Tsai

Chun-Hsiung Tsai

Chun-Hao Kung

Huai-Tei Yang

Chi-Jen Liu

Tang-Kuei Chang

Ziwei Fang

Yu-Sheng Wang

William Weilun Hong

Kao-Feng Liao

Chi-Hsiang Shen

Kuo-Feng Yu

Chun-Wei Hsu

Li-Chieh Wu

Jung-Chih Tsao

Te-Ming Kung

Shiu-Ko JangJian

Shih-Chieh Chang

Shich-Chang Suen

Chih-Chieh Chang

Ji Cui

Chien-Tai Chan

Tung-Kai Chen

Yang-Chun Cheng

Chii-Horng Li

Pei-Ren Jeng

Yi-Sheng Lin

Yu-Ku Lin

Shih-Ho Lin

Chia-Wei Ho

Ting-Hsun Chang

Chi-Cheng Hung

Min Hao Hong

Ting-Kui Chang

Ching-Hsiang Tsai

Huicheng Chang

Liang-Yin Chen

Chun-Chieh Lin

Yen-Ting Chen

Hsin-Ying Ho

Fu-Ming Huang

Te-Chien Hou

Shih-Tzung Chang

Su-Hao Liu

Tsan-Chun Wang

Kuo-Ju Chen

Szu-An Wu

Che-Hao Tu

Chih-Hung Chen

Ting-Chun Wang

Wen-Hsi Lee

Chia-Yang Wu

Ta-Chun Ma

Peng-Chung Jangjian

Yee-Chia Yeo

Chang-Miao Liu

Chia-Jung Hsu

Chien-Chang Su

Bwo-Ning Chen

Cheng-Yu Kuo

Yu-Ting Yen

Chi-Wen Liu

Chi-Cherng Jeng

Hsueh-Chang Sung

Ting-Chang Chang

Yen-Ru Lee

Chun-Chang Chen

Heng-Wen Ting

Chien-Wei Lee

Ying-Tsung Chen

Gin-Chen Huang

Chih-Chung Chang

Chun-An Lin

Kuan-Chang Chang

Chih-Hung Pan

Miao-Cheng Liao

Tsung-Ming Tsai

Ji-Yin Tsai

Wan-Chun Pan

Po-Jen Shih

Horng-Huei Tseng

Chih-Hao Chen

Chia-Cheng Chen

Ching-Hwanq Su

Chyi Shyuan Chern

Shih-Chi Lin

Lun-Kuang Tan

Wei-Ming You

Hung Jui Chang

Cheng-Po Chau

Wei-Jen Lo

Wen-Yu Ku

Pin-Ju Liang

Hsiang Hsiang Ko

A semiconductor device includes a source/drain region, a silicide region, a source/drain contact, and a silicon-containing dielectric liner. The source/drain region is in a substrate. The silicide region is embedded in the source/drain region. The source/drain contact is over the silicide region. The silicon-containing dielectric liner surrounds the source/drain contact. The source/drain region is in contact with an outer sidewall of the silicon-containing dielectric liner but separated from a bottom surface of the silicon-containing dielectric liner by the silicide region.

Semiconductor device with dielectric spacer liner on source/drain contact

A semiconductor structure includes a substrate, a nanowire disposed over the substrate, a metal gate electrode layer and a gate dielectric layer. A dielectric layer is formed on the substrate. The nanowire has a first portion and a second portion. The nanowire has a first portion and a second portion, the first portion of the nanowire comprises a first semiconductor layer and a second semiconductor layer surrounded by the first semiconductor layer, the second portion comprises the second semiconductor layer. The metal gate electrode layer surrounds the first portion of the nanowire. The gate dielectric layer is disposed between the metal gate electrode layer and the nanowire.

Semiconductor structure

Embodiments of the present disclosure relate a CMP tool and methods for planarization a substrate. Particularly, embodiments of the present disclosure provide a substrate transporter for use in a CMP tool. The transporter may be used transport and/or carry substrates among various polishers and cleaners in a CMP tool while preventing the substrates from drying out during transportation. By keeping surfaces of the substrates wet during substrate waiting time or idle time in the CMP tool, embodiments of the present disclosure prevent many types of defects, such as byproducts, agglomerated abrasives, pad debris, slurry residues, from accumulate on the substrate surface during CMP processing, thus improve yields and device performance.

Apparatus and methods for chemical mechanical polishing

Some implementations described herein relate to dispensing a slurry onto a polishing pad for a chemical-mechanical planarization (CMP) process. These implementations also involve rotating the polishing pad while the slurry is dispensed onto the polishing pad. Rotation of the polishing pad results in a traversal of the slurry radially outward toward a polishing pad outer edge of the polishing pad. The polishing pad includes a plurality of groove segments and a geometric patterns formed by the plurality of the groove segments impede the flow of the slurry to the polishing pad outer edge.

Chemical-mechanical planarization pad and methods of use

A chemical mechanical planarization (CMP) system including a capacitive deionization module (CDM) for removing ions from a solution and a method for using the same are disclosed. In an embodiment, an apparatus includes a planarization unit for planarizing a wafer; a cleaning unit for cleaning the wafer; a wafer transportation unit for transporting the wafer between the planarization unit and the cleaning unit; and a capacitive deionization module for removing ions from a solution used in at least one of the planarization unit or the cleaning unit.

CMP system and method of use

A tool and methods of removing films from bevel regions of wafers are disclosed. The bevel film removal tool includes an inner motor nested within an outer motor and a bevel brush secured to the outer motor. The bevel brush is adjustable radially outward to allow the wafer to be inserted in the bevel brush and to be secured to the inner motor. The bevel brush is adjustable radially inward to engage one or more sections of the bevel brush and to bring the bevel brush in contact with a bevel region of the wafer. Once engaged, a solution may be dispensed at the engaged sections of the bevel brush and the inner motor and the outer motor may be rotated such that the bevel brush is rotated against the wafer such that the bevel films of the wafer are both chemically and mechanically removed.

Bevel edge removal methods, tools, and systems

A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one cationic surfactant having at least one nitrogen atom in the molecule. The slurry includes at least one liquid carrier, at least one abrasive and at least one pH adjusting agent, and has a pH of less than 7.0. The polishing method includes using the slurry composition with the cationic surfactant to polish a conductive layer. The integrated circuit comprises a block layer comprising the cationic surfactant between a sidewall of the conductive plug and an interlayer dielectric layer.

Composition and method for polishing and integrated circuit

Methods of manufacturing a chemical-mechanical polishing (CMP) slurry and methods of performing CMP process on a substrate comprising metal features are described herein. The CMP slurry may be manufactured using a balanced concentration ratio of chelator additives to inhibitor additives, the ratio being determined based on an electro potential (Ev) value of a metal material of the substrate. The CMP process may be performed on the substrate based on the balanced concentration ratio of chelator additives to inhibitor additives of the CMP slurry.

Chemical mechanical polish slurry and method of manufacture

A polishing platform of a polishing apparatus includes a platen, a polishing pad, and an electric field element disposed between the platen and the polishing pad. The polishing apparatus further includes a controller configured to apply voltages to the electric field element. A first voltage is applied to the electric field element to attract charged particles of a polishing slurry toward the polishing pad. The attracted particles reduce overall topographic variation of a polishing surface presented to a workpiece for polishing. A second voltage is applied to the electric field element to attract additional charged particles of the polishing slurry toward the polishing pad. The additional attracted particles further reduce overall topographic variation of the polishing surface presented to the workpiece. A third voltage is applied to the electric field element to repel charged particles of the polishing slurry away from the polishing pad for improved cleaning thereof.

Chemical mechanical polishing apparatus and method

A method includes polishing a wafer on a polishing pad, performing conditioning on the polishing pad using a disk of a pad conditioner, and conducting a heat-exchange media into the disk. The heat-exchange media conducted into the disk has a temperature different from a temperature of the polishing pad.

Temperature control in chemical mechanical polish

A planarization method includes: providing a substrate, wherein the substrate includes a first region and a second region having different degrees of hydrophobicity or hydrophilicity, the second region covering an upper surface of the first region; polishing the substrate with a polishing slurry until the upper surface of the first region is exposed; and continuing polishing and performing a surface treatment by the polishing slurry to adjust the degree of hydrophobicity or hydrophilicity of at least one of the first region and the second region. The polishing slurry and the upper surface of the second region have a first contact angle, and the polishing slurry and the upper surface of the first region have a second contact angle. The surface treatment keeps a contact angle difference between the first contact angle and the second contact angle being equal to or less than 30 degrees during the polishing.

Chemical mechanical polishing method

A slurry composition, a polishing method and an integrated circuit are provided. The slurry composition includes a slurry and at least one rheology modifier. The slurry includes at least one liquid carrier, at least one abrasives and at least one oxidizer. The rheology modifier is dispensed in the slurry. The polishing method includes using the slurry composition with the rheology modifier to polish a conductive layer.

Slurry composition and method for polishing and integrated circuit

A chemical mechanical planarization system includes a chemical mechanical planarization pad that rotates during a chemical mechanical planarization process. A chemical mechanical planarization head places a semiconductor wafer in contact with the chemical mechanical planarization pad during the process. A slurry supply system supplies a slurry onto the pad during the process. A pad conditioner conditions the pad during the process. An impurity removal system removes debris and impurities from the slurry.

System and method for removing impurities during chemical mechanical planarization

A method for forming a semiconductor device structure is provided. The method includes forming a first metal layer over a substrate, forming a dielectric layer over the first metal layer. The method includes forming a trench in the dielectric layer, and performing a surface treatment process on a sidewall surface of the trench to form a hydrophobic layer. The hydrophobic layer is formed on a sidewall surface of the dielectric layer. The method further includes depositing a metal material in the trench and over the hydrophobic layer to form a via structure.

Semiconductor device structure with an interconnect structure in a dielectric layer with multiple hydrophobic layers along sidewalls of the dielectric layer, and method for forming the same

A method includes cropping a plurality of images from a layout of an integrated circuit, generating a first plurality of hash values, each from one of the plurality of images, loading a second plurality of hash values stored in a hotspot library, and comparing each of the first plurality of hash values with each of the second plurality of hash values. The step of comparing includes calculating a similarity value between the each of the first plurality of hash values and the each of the second plurality of hash values. The method further includes comparing the similarity value with a pre-determined threshold similarity value, and in response to a result that the similarity value is greater than the pre-determined threshold similarity value, recording a position of a corresponding image that has the result. The position is the position of the corresponding image in the layout.

Hotspot avoidance method of manufacturing integrated circuits

Growing community of inventors

Tainan, Taiwan

Kei-Wei Chen