Osaka University

Naxfi Technology Inc.

Kei Nishioka

Takashi Nakamura

Tsuyoshi Funaki

Toshio Hanada

A power substrate () of the present invention includes a plurality of insulating substrates () arranged side by side along a plurality of current paths (P) extending in the same direction, a plurality of MOS transistors () mounted on one major surface of each of the plurality of insulating substrates () with a first conductive layer () and a first solder bonding layer () in between, and a heat dissipation member () in contact with other major surfaces of all of the insulating substrates with a second conductive layer () and a second solder bonding layer () in between, and each of the current paths (P) is formed by connecting one or more of the MOS transistors () mounted on one of the insulating substrates () with one or more of the MOS transistors () mounted on a different one of the insulating substrates () in series with each other.

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Suita, Japan

Kei Nishioka