Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Kei Hamade

Mikio Asakura

Kiyohiro Furutani

Tsukasa Ooishi

Hideto Hidaka

Takashi Kono

Takeshi Hamamoto

Kenichi Yasuda

Tetsuo Kato

Yoshito Nakaoka

Tadaaki Yamauchi

Yasuhiro Konishi

Shigeru Mori

Masaru Haraguchi

Yoshikazu Morooka

Yuichiro Komiya

Yasuhiro Matsumoto

In a multi-bit test, an I/O combiner degenerates data of a plurality of bits read from a memory cell array to first to fourth data bus pairs in parallel and outputs the degenerated data to a fifth data bus. A read amplifier compares a logic level of the degenerated data received from the I/O combiner with a logic level of expected value data. If the logic level of the degenerated data coincides with the logic level of the expected value data, the read amplifier determines that data write and read to and from the plurality of bits have been normally performed. As a result, a semiconductor memory device can detect a word line defect in the multi-bit test.

Semiconductor memory device having multi-bit testing function

Pads are alignedly arranged in a central region of a semiconductor chip and are also arranged at an outer peripheral portion of the central portion of the chip. A pad at the outer peripheral portion is electrically connected to a die pad mounting the chip thereon with an insulative material interposed therebetween. A potential supplied to the pad positioned at the outer peripheral portion can be stabilized by parasitic capacitance of the die pad, and a potential of the die pad can be externally monitored easily by removing away a portion of mold resin after resin sealing. Further, due to a cress shaped arrangement of the pads, a voltage down converter can be arranged in line with the pads and at outer periphery of the chip without area penalty. In testing operation, a switching circuit switches a function of a pad to another pad so that cross-shapedly arranged pads are equivalently arranged in a line.

Semiconductor device with efficiently arranged pads

In the SDRAM, a selector selects one of four global IO line pairs according to a column block select signal and a word configuration selecting signal, and connects the selected global IO line pair to an input/output node pair of a preamplifier in a pulsed manner for a prescribed period of time. Since the equalization of the global IO line pair can be started immediately after the global IO line pair is connected in a pulsed manner to the input/output node pair of the preamplifier, longer equalization period for the global IO line can be set aside so that the read operation can be stabilized.

Semiconductor memory device

A circuit generating a test mode instructing signal includes a test mode register circuit which is set to a state disabling instruction of a test mode in a standby state. An intended test mode can be accurately selected even when the test mode is instructed in accordance with a plurality of external signals varied in timing from each other. A semiconductor device allows accurate and efficient execution of the test without requiring increase in area occupied by an array.

Semiconductor device operable in a plurality of test operation modes

First and second global input/output lines are twisted between first and second main blocks. First and second SD signal lines in the first main block are respectively arranged adjacent to first and second global input/output lines. First and second SD signal lines in the second main block are respectively arranged adjacent to the second and first global input/output lines. An SD signal supplied for the first or second SD signal line makes noises applied to the first and second global input/output lines identical, so that an influence by the noises is substantially eliminated between the first and second global input/output lines. As a result, the global input/output line is provided with higher resistance to noise without any increase in a layout area.

Semiconductor memory device having hierarchical word line structure

A circuit for supplying a stress to memory cells of a semiconductor memory device having the plurality of the memory cells respectively connected to a word line and a bit line comprises a circuit for generating precharge voltage for bit line, a bit line precharging and equalizing circuit which is connected between said circuit for generating precharge voltage for bit line and said memory cells, a pad connected to the bit line precharging and equalizing circuit for applying a desirable voltage to said memory cells through the corresponding bit lines, and a circuit connected to the circuit for generating precharge voltage for bit line for generating a signal for stopping the operation of said circuit for generating precharge voltage for bit line, whereby cell checker patterns can easily be realized in order to screen out possible failures not only in gate oxide films but also in capacitor dielectrics, storage node junctions or the like by applying an arbitrary stress voltage from the outside of the device.

Test circuit for a semiconductor memory device and method for burn-in

Read drivers which are provided in correspondence to simultaneously selected plural bits of memory cells are wired-OR connected to internal read data buses which in turn are provided in correspondence to a plurality of memory cell arrays respectively. A test mode circuit is provided for the internal read data buses for detecting coincidence/incoincidence of logics of signal potentials on these internal read data bus lines. In a test operation, all read drivers are activated to read selected memory cell data on the corresponding internal read data bus lines.

Semiconductor memory device having data input/output circuit of small

A sense amplifier (2) is connected to an input/output circuit (7), transmitting input/output data therebetween. The input/output circuit (7) is connected to an address scramble circuit (8). Furthermore, the input/output circuit (7) is connected to a data input/output terminal (DIO), externally transmitting data. The address scramble circuit (8) receives input data (INTDQ) from the data input/output terminal (DIO) and converts the input data (INTDQ) into write data (WD) in accordance with the layout of memory cells in a memory array (1) in response to a burn-in mode signal (BIT) outputted from an address key circuit (9) and a row address first signal RAF outputted from a row address buffer (6). Having the above configuration, a semiconductor memory device can be provided, which permits a prescribed stress to be imposed on its internal circuit only by inputting simple data even in a burn-in test. Moreover, a semiconductor memory device can be provided, which allows an external verification as to whether the device itself enters a burn-in mode or not.

In a memory plane of a semiconductor memory device, transmission gate circuits for transferring data between local I/O line pair and global I/O line pair, and equalizing circuits for equalizing the local I/O line pair are arranged alternately on both sides of a shunt region. All the global I/O line pairs extend entirely over the memory plane. One and the other global I/O lines are arranged in symmetry, with a line for transmitting bit line precharge voltage, cell plate voltage or local input/output line equalizing signal being the center.

Semiconductor memory device having improved hierarchical I/O line pair

An internal address signal is outputted quickly by connecting nMOS transistors in series to inverters forming a latching circuit of a row address buffer circuit, applying an external row address signal to the gate of a nMOS transistor, applying a delayed activation signal .phi.2 to the gate of the nMOS transistors, grounding the gate of the nMOS transistor, triggering nMOS transistors into complete conduction by the delayed activation signal .phi.2 to reduce the ON resistance. A column address buffer circuit receives a ZCAS circuit by an NOR gate, and an external column address signal by an NAND gate during standby, to prevent a flow of a through current.

Buffer circuit of a semiconductor memory device

Separated IO type dynamic memory device includes a write data bus for transmitting data to be written into a selected memory cell and a read data bus for transferring data read out from a selected memory cell. The write data bus and the read data bus are separately provided from each other. The memory device further includes a load circuit for supplying a current flow to the read data bus and for precharging the read data bus to a predetermined potential, and drive circuits provided for each pair of bit lines each connecting memory cells of a column for driving the read data bus to a potential corresponding to potentials appearing on an associated pair of bit lines in response to a column select signal. The memory device further includes an insulated gate type transistor inserted on the read data bus between the loading circuit and the driving circuits and receives a predetermined intermediate potential at the gate. An output node for supplying an output data is provided between the insulated gate type transistor and the load circuit. This enables fast discharging of the read data bus at the output node, resulting in a high speed data reading operation.

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Hyogo, Japan

Kei Hamade