International Business Machines Corporation

Globalfoundries Inc.

Samsung Electronics Co., Ltd.

Kehan Tian

Alan Edward Rosenbluth

David Osmond Melville

Tadanobu Inoue

Masaharu Sakamoto

Saeed Reza Bagheri

Kafai Lai

Hidemasa Muta

David O S Melville

Chieh-Yu Lin

Zheng Xu

Dongbing Shao

Jaione Tirapu Azpiroz

Kangguo Cheng

Bruce Bennett Doris

Ali Khakifirooz

Rajiv V Joshi

Shom Ponoth

Reinaldo Ariel Vega

Kern Rim

Herbert Lei Ho

Ying Liu

John Edward Barth, Jr

Babar Ali Khan

Fook-Luen Heng

Rama Nand Singh

Saibal Mukhopadhyay

Jonathan Lee

Marc Alan Szeto-Millstone

Andreas Waechter

Masahura Sakamoto

Sanghoon Baek

Maria Gabrani

Dario Gil

David L DeMaris

Francisco Barahona

Jaione Tirapu-Azpiroz

Laszlo Ladanyi

Daniele P Scarpazza

Technical solutions are described for fabricating a semiconductor wafer. An example method includes generating a process assumption band for an element of the wafer. The process assumption band depicts a shape of the element based on a set of process variations in a photolithographic process used for fabricating the wafer. The method also includes generating a process variation band for the element of the wafer based on optical process correction simulation of the photolithographic process using design rules associated with the wafer. The method also includes determining a deviation between the process assumption band and the process variation band, and recalculating one or more design rules from the design rules associated with the wafer based on the deviation. The method also includes updating the design of the wafer in response to the process variation band not being changeable to match the process assumption band, after recalculating the design rules.

Semiconductor fabrication design rule loophole checking for design for manufacturability optimization

A system and method for optimizing (designing) a mask pattern, in which SMO and OPC are collaboratively used to exert a sufficient collaborative effect or are appropriately used in different manners. The method for designing a source and a mask for lithography includes a step (S) of selecting a set of patterns; a step of performing source mask optimization (SMO) using the set of patterns, under an optical proximity correction (OPC) restriction rule which is used for selectively restricting shifting of an edge position of a polygon when OPC is applied to the set of patterns; and a step (S, S) of determining a layout of the mask for lithography, by applying OPC to all patterns constituting the mask for lithography using the source optimized through the SMO.

Method and program product for designing source and mask for lithography

Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Dummy gate structure for electrical isolation of a fin DRAM

Methods and systems for determining a source shape, a mask shape and a target shape for a lithography process are disclosed. One such method includes receiving source, mask and target constraints and formulating an optimization problem that is based on the source, mask and target constraints and incorporates contour-based assessments for the target shape that are based on physical design quality of a circuit. Further, the optimization problem is solved by integrating over process condition variations to simultaneously determine the source shape, the mask shape and the target shape. In addition, the determined source shape and mask shape are output.

Source, target and mask optimization by incorporating contour based assessments and integration over process variations

In one embodiment, a source mask optimization (SMO) method is provided that includes controlling bright region efficiency during at least one optical domain step. The bright region efficiency being the proportion of the total transmitted light that is transferred to bright areas of a target pattern. The optical domain intermediate solution provided by the at least one optical domain step may then be binarized to obtain an initial spatial domain solution with a controlled MEEF (Mask Error Enhancement Factor). The MEEF is controlled during at least one spatial domain step that optimizes the initial spatial domain solution.

Synthesizing low mask error enhancement factor lithography solutions

Source, target and mask optimization by incorporating countour based assessments and integration over process variations

A design layout includes a set of active region-level design shapes representing semiconductor active regions, and a set of gate-level design shapes representing gate lines straddling the semiconductor active regions. The set of gate-level design shapes include a sub-resolution assist feature (SRAF) that connects two gate-level design shapes, and is physically manifested as a gap between two gate lines upon printing employing lithographic methods. An edge of a gate line in proximity to a semiconductor active region can be cut employing a cut mask that includes a cut-level design shape that has a protruding tap. The protruding tap allows reliable removal of an end portion of a gate line and prevents disruption of raised source and drain regions by an unwanted residual gate structure.

High density field effect transistor design including a broken gate line

A method, an article of manufacture, and a system for designing a mask. The method for designing a mask is implemented by a computer device having a memory, a processor device communicatively coupled to the memory, and a module configured to carry out the method including the steps of: generating an optical domain representation from a design pattern and an imaging light; and optimizing the optical domain representation under a constraint that values of negative excursions at predetermined evaluation points must be greater than or equal to predetermined negative threshold values assigned to the predetermined evaluation points; where: the optical domain representation is a variable representation of a wavefront; the imaging light is light that is transmitted through the mask; the negative excursions are in an object domain representation of the optical domain representation; and the predetermined evaluation points are in the object domain representation.

Mask design method, program, and mask design system

Systems and methods for optimizing a source shape and a mask shape for a lithography process are disclosed. One such method includes performing a mask optimization for the lithography process in accordance with a set of parameters including at least one variable representation, at least one objective and problem constraints. Further, a light source optimization for the lithography process is performed in accordance with the set of parameters. In addition, a joint light source-mask optimization is performed in accordance with the set of parameters. The method further includes iterating at least one of the mask optimization or the light source optimization by changing at least one of the variable representation, the objective or the problem constraints to maximize a common process window for the lithography process.

Source-mask optimization for a lithography process

Techniques are presented that include accessing results of forward simulations of circuit yield, the results including at least circuit yield results including simulated device shapes. Using the circuit yield results, high-level traits of at least the simulated device shapes are determined. Based on the determined high-level traits and using the circuit yield results, a compact model for predicted yield is constructed, the compact model including a plurality of adjustable parameters, and the constructing the compact model for predicted yield including adjusting the adjustable parameters until at least one first predetermined criterion is met. An optimization problem is constructed including at least the compact model for yield, an objective, and a plurality of constraints. Using the optimization problem, the objective is modified subject to the plurality of constraints until at least one second predetermined criterion is met.

Analyzing a patterning process using a model of yield

Mask layout data of a lithographic mask includes polygons that each include horizontal and vertical edges. Each of a number of target edge pairs is defined by two edges of one or more of the polygons. A search box having a boundary coincident with a given edge of the edges of the polygons is specified. Whether the search box includes at least one edge of the edges of the polygons in addition to the given edge is determined. Where the search box includes at least one edge, at least one of the target edge pairs is specified as including the given edge and one of the at least one edge. For each target edge pair that has been specified, a manufacturability penalty value is determined. A dynamic manufacturability constraint table and a non-zero multiplier table are maintained.

Optimizing lithographic mask for manufacturability in efficient manner

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Poughkeepsie, NY, United States of America

Kehan Tian