Rockwell International Corporation

Keh-Fei C Chi

Robert L Zwingman

Pei-Ming D Chow

Karen A Reinhardt

Yau-Wai D Chan

Rebecca Y Tang

Patricia C Elkins

A method of providing a planar or iso-planar surface to the interlevel dielectric layer between metal layers of a multilevel MOS wafer includes applying a first dielectric over the first metal layer, applying a layer of spin-on glass over the first dielectric layer, etching the spin-on glass layer in an etch process in which the rate of etch of the spin-on glass is approximately the same as the rate of etch of the first dielectric to reveal at least a portion of the first dielectric layer. A second dielectric layer is placed over the surface of the first dielectric. Vias may then be defined through the dielectric layers, and the second metal layer may be applied over the relatively smooth surface of the second dielectric layer.

Planarization process for double metal MOS using spin-on glass as a

A method of visually monitoring the change in dimensions of elements on a surface of a semiconductor body during processing is provided. A fixed pattern of scale images on the surface with a predetermined distance between images, together with a wedge-shaped element is provided on the surface. The wedge element has an apex adjacent one of the images and extends in a direction along other ones of the images. The semiconductor body is processed and the dimensions of the wedge-shaped element (as well as the scale image) change. One may then subsequently visually inspect the wedge shaped element with respect to the pattern of images to determine the extent of the change in dimension of the wedge shaped element during processing.

Dimension monitoring technique for semiconductor fabrication

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Garden Grove, CA, United States of America

Keh-Fei C Chi