Taiwan Semiconductor Manufacturing Comp. Ltd.

Keh-Chiang Ku

Chun-Feng Nieh

Li-Ting Wang

Chien-Hao Chen

Tze-Liang Lee

Shih-Chang Chen

Cheng-Lung Hung

Nai-Han Cheng

Chien-Hao Huang

Li-Te S Lin

Yu-Chang Lin

Chi-Chun Chen

Li-Ping Huang

Yong-Tian Hou

Hsun Chang

Kong-Beng Thei

Harry Chuang

Pang-Yen Tsai

Mong Song Liang

Hung-Chih Tsai

Chih-Chiang Wang

Wenli Lin

A device and a method for forming a metal silicide is presented. A device, which includes a gate region, a source region, and a drain region, is formed on a substrate. A metal is disposed on the substrate, followed by a first anneal, forming a metal silicide on at least one of the gate region, the source region, and the drain region. The unreacted metal is removed from the substrate. The metal silicide is implanted with atoms. The implant is followed by a super anneal of the substrate.

Implanted metal silicide for semiconductor device

A semiconductor device includes a semiconductor substrate and a transistor formed in the substrate, the transistor having a gate stack that has an interfacial layer formed on the substrate, a high-k dielectric layer formed over the interfacial layer, a metal layer formed over the high-dielectric layer, a capping layer formed between the interfacial layer and high-k dielectric layer; and a doped layer formed on the metal layer, the doped layer including at least F.

High-k metal gate device

A semiconductor structure comprises a gate stack in a semiconductor substrate and a lightly doped source/drain (LDD) region in the semiconductor substrate. The LDD region is adjacent to a region underlying the gate stack. The LDD region comprises carbon and an n-type impurity, and the n-type impurity comprises phosphorus tetramer.

Shallow junction formation and high dopant activation rate of MOS devices

An annealing method includes performing an activation annealing on a wafer with a peak temperature of greater than about 1200&#xb0; C., wherein the activation annealing has a first duration; and performing a defect-recovery annealing on the wafer at a defect-recovery temperature lower than the peak temperature for a second duration. The second duration is longer than the first duration. The annealing method includes no additional annealing steps at temperatures greater than about 1200&#xb0; C., and no room-temperature cooling step exists between the activation annealing and the defect-recovery annealing.

Junction profile engineering using staged thermal annealing

A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate stack over the semiconductor substrate; implanting carbon into the semiconductor substrate; and implanting an n-type impurity into the semiconductor substrate to form a lightly doped source/drain (LDD) region, wherein the n-type impurity comprises more than one phosphorous atom. The n-type impurity may include phosphorous dimer or phosphorous tetramer.

The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a high-k dielectric layer over a semiconductor substrate, forming a capping layer over the high-k dielectric layer, forming a metal layer over the capping layer, forming a semiconductor layer over the metal layer, performing an implantation process on the semiconductor layer, the implantation process using a species including F, and forming a gate structure from the plurality of layers including the high-k dielectric layer, capping layer, metal layer, and semiconductor layer.

Implantation method for reducing threshold voltage for high-K metal gate device

A semiconductor device includes a gate stack over a semiconductor substrate, a lightly doped n-type source/drain (LDD) region in the semiconductor substrate and adjacent the gate stack wherein the LDD region comprises an n-type impurity, a heavily doped n-type source/drain (N+ S/D) region in the semiconductor substrate and adjacent the gate stack wherein the N+ S/D region comprises an n-type impurity, a pre-amorphized implantation (PAI) region in the semiconductor substrate wherein the PAI region comprises an end of range (EOR) region, and an interstitial blocker region in the semiconductor substrate wherein the interstitial blocker region has a depth greater than a depth of the LDD region but less than a depth of the EOR region.

Semiconductor device having ultra-shallow and highly activated source/drain extensions

A method for forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric layer over the semiconductor substrate; forming a gate electrode layer over the gate dielectric layer; doping carbon and nitrogen into the gate electrode layer; and, after the step of doping carbon and nitrogen, patterning the gate dielectric layer and the gate electrode layer to form a gate dielectric and a gate electrode, respectively.

Reducing poly-depletion through co-implanting carbon and nitrogen

A method for forming a semiconductor structure includes providing a semiconductor substrate, forming a gate stack on the semiconductor substrate, and epitaxially growing a lightly-doped source/drain (LDD) region adjacent the gate stack, wherein carbon is simultaneously doped into the LDD region.

Short channel effect engineering in MOS device using epitaxially carbon-doped silicon

A method of forming a semiconductor structure includes providing a semiconductor substrate; forming a gate dielectric over the semiconductor substrate; forming a gate electrode on the gate dielectric; forming a source/drain region adjacent the gate dielectric and the gate electrode; forming an absorption-capping layer over the source/drain region and the gate electrode; performing an activation by applying a high-energy light to the absorption-capping layer; and removing the absorption-capping layer.

Advanced activation approach for MOS devices

A method for forming a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a gate dielectric over the semiconductor substrate, forming a gate electrode on the gate dielectric, forming a stressor in the semiconductor substrate adjacent an edge of the gate electrode, and implanting an impurity after the step of forming the stressor. The impurity is preferably selected from the group consisting essentially of group IV elements, inert elements, and combinations thereof.

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Sindan, Taiwan

Keh-Chiang Ku