Omnivision Technologies, Inc.

Keh-Chiang Ku

Vincent Venezia

Duli Mao

Hsin-Chih Tai

Yin Qian

Howard E Rhodes

Wei Zheng

Chia-Ying Liu

Gang Chen

Wu-Zhang Yang

Dyson Hsinchih Tai

Sohei Manabe

Sing-Chung Hu

Manoj Bikumandla

Zhibin Xiong

Embodiments of an image sensor pixel that includes a photosensitive element, a floating diffusion region, and a transfer device. The photosensitive element is disposed in a substrate layer for accumulating an image charge in response to light. The floating diffusion region is dispose in the substrate layer to receive the image charge from the photosensitive element. The transfer device is disposed between the photosensitive element and the floating diffusion region to selectively transfer the image charge from the photosensitive element to the floating diffusion region. The transfer device includes a buried channel device including a buried channel gate disposed over a buried channel dopant region. The transfer device also includes a surface channel device including a surface channel gate disposed over a surface channel region. The surface channel device is in series with the buried channel device. The surface channel gate has the opposite polarity of the buried channel gate.

Partial buried channel transfer device for image sensors

Techniques and mechanisms for improving full well capacity for pixel structures in an image sensor. In an embodiment, a first pixel structure of the image sensor includes an implant region, where a skew of the implant region corresponds to an implant angle, and a second pixel structure of the image sensor includes a transfer gate. In another embodiment, an offset of the implant region of the first pixel structure from the transfer gate of the second pixel structure corresponds to the implant angle.

Method, apparatus and system for providing improved full well capacity in an image sensor pixel

Methods of forming isolation structures are disclosed. A method of forming isolation structures for an image sensor array of one aspect may include forming a dielectric layer over a semiconductor substrate. Narrow, tall dielectric isolation structures may be formed from the dielectric layer. The narrow, tall dielectric isolation structures may have a width that is no more than 0.3 micrometers and a height that is at least 1.5 micrometers. A semiconductor material may be epitaxially grown around the narrow, tall dielectric isolation structures. Other methods and apparatus are also disclosed.

Etching narrow, tall dielectric isolation structures from a dielectric layer

Embodiments of a semiconductor device that includes a semiconductor substrate and a cavity disposed in the semiconductor substrate that extends at least from a first side of the semiconductor substrate to a second side of the semiconductor substrate. The semiconductor device also includes an insulation layer disposed over the first side of the semiconductor substrate and coating sidewalls of the cavity. A conductive layer including a bonding pad is disposed over the insulation layer. The conductive layer extends into the cavity and connects to a metal stack disposed below the second side of the semiconductor substrate. A through silicon via pad is disposed below the second side of the semiconductor substrate and connected to the metal stack. The through silicon via pad is position to accept a through silicon via.

Pad design for circuit under pad in semiconductor devices

A method of fabricating a backside-illuminated pixel. The method includes forming frontside components of the pixel on or in a front side of a substrate, the frontside components including a photosensitive region of a first polarity. The method further includes forming a pure dopant region of a second polarity on a back side of the substrate, applying a laser pulse to the backside of the substrate to melt the pure dopant region, and recrystallizing the pure dopant region to form a backside doped layer. Corresponding apparatus embodiments are disclosed and claimed.

Method of damage-free impurity doping for CMOS image sensors

An isolation area that provides additional active area between semiconductor devices on an integrated circuit is described. In one embodiment, the invention includes a complementary metal oxide semiconductor transistor of an image sensor having a source, a drain, and a gate between the source and the drain, the transistor having a channel to couple the source and the drain under the influence of the gate, and an isolation barrier surrounding a periphery of the source and the drain to isolate the source and the drain from other devices, wherein the isolation barrier is distanced from the central portion of the channel.

Isolation area between semiconductor devices having additional active area

A backside illuminated imaging sensor with a seal ring support includes an epitaxial layer having an imaging array formed in a front side of the epitaxial layer. A metal stack is coupled to the front side of the epitaxial layer, wherein the metal stack includes a seal ring formed in an edge region of the imaging sensor. An opening is included that extends from the back side of the epitaxial layer to a metal pad of the seal ring to expose the metal pad. The seal ring support is disposed on the metal pad and within the opening to structurally support the seal ring.

Seal ring support for backside illuminated image sensor

Embodiments of a method for separating dies from a wafer having first and second sides. The process embodiment includes masking the first side of the wafer, the mask including openings therein to expose parts of the first side substantially aligned with scribe lines of the wafer. The process embodiment also includes etching from the exposed parts of the first side of the wafer until an intermediate position between the first and second sides and sawing the remainder of the wafer, starting from the intermediate position until reaching the second surface.

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Cupertino, CA, United States of America

Keh-Chiang Ku