Broadcom Corporation

Keh-Chee Jen

Hongtao Jiang

Tuan Hoang

Nong Fan

Khorvish Sefidvash

A system () includes a communication path () and transmits data on a network (). A transmitter () transmits data on the network and a receiver () receives data from the network. A component () in the communication path has a transfer characteristic (C, C, C) adjusted in response to errors in data transmitted over and received from the network in order to reduce the error rate.

Bit error rate based system and method for optimizing communication system performance

Aspects of the invention provide a method and system for reducing signal distortion within an on-chip transitive module. In response to receipt of a signal bearing at least one external clock frequency, at least one harmonic signal of the signal bearing the at least one external clock frequency may be generated. At least one synchronization clock frequency signal may be created from the generated at least one harmonic signal. The synchronization clock frequency signal may subsequently be supplied to at least one power source. Accordingly, the at least one power source may serve as an input power source to at least one on-chip system component of the transitive module with. In this regard, an output of the at least one power source may have at least a frequency attribute of the synchronization clock frequency signal. The synchronization clock frequency signal may reduce signal distortion produced by the at least one power source.

System and method for performing on-chip synchronization of system signals utilizing off-chip harmonic signal

Aspects of the invention provide a method end system for reducing signal distortion within an on-chip transceiver module. In response to receipt of a signal bearing at least one external clock frequency, at least one harmonic signal of the signal bearing the at least one external clock frequency may be generated. At least one synchronization clock frequency signal may be created from the generated at least one harmonic signal. The synchronization clock frequency signal may subsequently be supplied to at least one power source. Accordingly, the at least one power source may serve as an input power source to at least one on-chip system component of the transceiver module. In this regard, an output of the at least one power source may have at least a frequency attribute of the synchronization clock frequency signal. The synchronization clock frequency signal may reduce signal distortion produced by the at least one power source.

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Las Flores, CA, United States of America

Keh-Chee Jen