Samsung Electronics Co., Ltd.

Sungkyunkwan University

Keewon Kwon

Jaechul Park

Youngsoo Park

Seungeon Ahn

Seunghoon Lee

Chaehwan Park

Jongmin Baek

Dongjin Seo

Sangwon Kim

Myoungjae Lee

Youngwug Kim

Sewon Yun

A bit line sense amplifier includes a differential amplifier configured to receive an input signal from a bit line through an input terminal of the bit line sense amplifier and output a first signal to a first node of the bit line sense amplifier, a sensing inverter configured to receive the first signal and output a second signal to a second node of the bit line sense amplifier, the second signal resulting from inverting the first signal, a first switch configured to electrically connect the second node to a positive input of the differential amplifier, a second switch configured to electrically connect the first node to the positive input of the differential amplifier, and a third switch configured to electrically connect the second node to a negative input of the differential amplifier.

Bit line sense amplifier and bit line sensing method of semiconductor memory device

A bit line sense amplifier includes: a first inverter configured to receive an input signal from a bit line via an input terminal and output a first signal to a first node; a second inverter configured to receive the first signal and output a second signal to a second node; a differential amplifier configured to receive the input signal as a positive input, and receive the second signal as a negative input; and a first switch configured to electrically connect the input terminal to the positive input of the differential amplifier and a second switch configured to electrically connect the second node to the negative input of the differential amplifier.

Disclosed is an electronic device which includes processing elements arranged in rows and columns, word lines connected with the rows of the processing elements, bit lines connected with the columns of the processing elements, body lines connected with the columns of the processing elements, and source lines connected with the rows of the processing elements. Each of the processing elements includes a first terminal connected with a corresponding bit line of the bit lines, a second terminal connected with a corresponding source line of the source lines, a control gate connected with a corresponding word line of the word lines, a floating gate between the control gate and a body, a body terminal connected with a corresponding body line of the body lines, and a capacitive element between the floating gate and the corresponding bit line.

Processing element and electronic device including processing element

Disclosed are a semiconductor memory apparatus, a program method, and a program system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells and a control block configured to variably control, based on digital code values reflecting resistance states of the resistive memory cells, at least one of a initial voltage magnitude and an initial voltage applying time in an incremental step pulse programming (ISPP) mode for the plurality of memory cells. Therefore, even in the case of the worst cell, the incremental step of the ISPP may be minimized, and the writing time may be reduced, limiting unnecessary current consumption.

Resistive semiconductor memory capable of performing incremental step pulse programming (ISPP) based on digital code values of memory cells

Disclosed are a semiconductor memory apparatus, and verify read method and system. The semiconductor memory apparatus includes a memory cell array including a plurality of resistive memory cells; and a control block controlling a resistance state of the memory cell to be discriminated based on a digital code value of at least 2 bits or more reflecting the resistance states of the plurality of resistive memory cells. Therefore, data of the memory is discriminated by analyzing distribution of the digital code values to monitor a characteristic of a current memory cell array and read the data having reliability.

Semiconductor memory device and method for reading the same using a memory cell array including resistive memory cells to perform a single read command

A multi-layered memory device is provided. The multi-layered memory device includes two or more memory units and an active circuit unit arranged between each of the two or more memory units. The active circuit includes a decoder. Each memory unit includes one or more memory layers. Each memory layer includes a memory array.

Multi-layered memory devices

A transistor having a self-align top gate structure and methods of manufacturing the same are provided. The transistor includes an oxide semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region. The transistor further includes a gate insulating layer and a gate electrode, which are sequentially stacked on the channel region. Semiconductor devices including at least one transistor and methods of manufacturing the same are also provided.

Transistors, semiconductor devices and methods of manufacturing the same

Example embodiments provide a method of operating a non-volatile memory in which the non-volatile memory may only be changed from a first state to a second state and may not be changed from the second state to the first state during a programming operation.

Operation method of non-volatile memory

A high dielectric constant film comprised of at least a first dual-film layer, which includes a first tantalum oxide film, and a first metal oxide film which is made of a metal oxide whose valence is smaller than that of tantalum, and whose dielectric constant is equal to or greater than that of tantalum oxide. The first metal oxide film preferably has a thickness of less than approximately 50 angstroms, in order to thereby avoid the formation of a columnar structure, which has been identified as a principal cause of the high leakage current problem which has plagued presently available high dielectric constant capacitors. The first tantalum oxide film preferably has a thickness in the range of between approximately 5 angstroms to approximately 200 angstroms, with the ratio of the thickness of the first tantalum oxide film to the thickness of the first metal oxide film being in the range of 1:10 to 100:1. The high dielectric constant film preferably further includes a plurality of additional dual-film layers formed on the first dual-film layer, to thereby provide a multilayer high dielectric constant film. Each of the additional dual-film layers is preferably of the same construction as that of the first dual-film layer. The present invention also encompasses a high dielectric constant capacitor which incorporates the above-described high dielectric constant film, and a method for manufacturing the same.

Growing community of inventors

Seongnam-si, South Korea

Keewon Kwon