International Business Machines Corporation

Keenan Wynn Franz

Ravi Kumar Arimilli

Derek E Williams

Michael Thomas Vaden

David Benjamin Shuler

Daniel Mark Dreps

Robert K Mullady

Edward Joseph Seminaro

Kevin Franklin Reick

Nam Huu Pham

Lloyd Andre Walls

Raymond A Longhi

John David Purcell

A memory system is deigned for impedance matching using a network of resistors that are tuned to reduce reflections on a shared bus. Any deviation from the matched state causes a mismatch and results in reflections on the bus. Overall signal reflections are reduced by balancing the back reflections occurring at a connector junction coupled to a pair of resistors and the back reflections occurring at the input of the DIMMs. This balance or tradeoff is achieved by changing the resistance value of the resistor pair to reduce the overall back reflections in the memory system.

Impedance matching system for DDR memory

A server including a cooling fan assembly and an input/output assembly at opposite ends of the server, and a processor assembly located between the cooling fan assembly and input/output assembly. The server also includes a cover plate that covers the processor assembly and cooling fan assembly and that has a power supply on the face of the cover plate facing the processor assembly and is electrically connected to the processor assembly.

Ultra dense multipurpose server

A processor card for supporting multiple cache configurations, and a microprocessor for selecting one of the multiple cache configurations is disclosed. The processor card has a first static random access memory mounted on a front side thereof and a second static random access memory mounted on a rear side thereof. The address pins of the memories are aligned. Each pair of aligned address pins are electrically coupled to thereby concurrently receive an address bit signal from the microprocessor. During an initial boot of the microprocessor, the microprocessor includes a multiplexor for providing the address bit signals to the address pins in response to a control signal indicative of a selected cache configuration.

Method and system for supporting multiple cache configurations

A method and system for verifying a correct orientation of a module during installation of the module into a circuit board mounting site. The module housing is symmetric in at least one respect such that the module may be positioned in at least one alternate orientation with respect to the mounting site in addition to the correct orientation. Within the module, a module test contact is electrically connected to a common plane mode contact. A mounting site test contact that engages the module test pin when the module is correctly aligned with respect to the mounting site is preselected to be tested upon placement of the module onto the mounting site. A test signal is applied to a conductive common plane within the mounting site to which a common plane mounting site contact is connected. Prior to installation of the module into the mounting site, the mounting site test contact is electrically isolated from the conductive common plane to which a test signal is applied. The module is tentatively connected to the mounting site. Upon connection of the module, only the mounting site test contact is tested to ensure that the module has been correctly positioned within respect to the mounting site.

Non-destructive module placement verification

An apparatus and method for monitoring an internal communication path, i.e. an internal bus, of an integrated circuit is described. The internal bus operates at a particular frequency, f,. An image of the internal bus is produced, operating at a lower frequency of operations, f,, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be &ldquo;out-of-phase&rdquo; with respect to one another. A buffer/align unit processes the signals in order to produce a time delayed version of the signals. The buffer/aliqn unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, f,. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, f,.

Method and apparatus for monitoring internal bus signals by using a reduced image of the internal bus

An apparatus and method for monitoring a PowerPC 60x bus within an integrated circuit is described. The 60x bus operates at a particular frequency, f.sub.b. An image of the 60x bus is produced, operating at a lower frequency of operations, f.sub.o, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Masking circuitry within the driver/receiver circuitry masks bi-directional signals, such as ARTRY.sub.-- and SHD.sub.--, during the pre-charge cycles, when these bi-directional signals are in an unpredictable state. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be 'out-of-phase' with respect to one another. A buffer/align unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, f.sub.o. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, f.sub.o.

Method and apparatus for monitoring 60x bus signals at a reduced

A system and method for allowing different operating systems to be utilized in a multiprocessing system is provided in which each of the different operating systems requires different types of interrupt controllers. The system and method comprises detecting which of the at least two different types of operating systems is utilized within the multiprocessing system, and then selecting the appropriate interrupt controller from the different types of interrupt controllers.

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Austin, TX, United States of America

Keenan Wynn Franz