Altera Corporation

Keen Yew Loke

Siew Leong Lam

Paul B Ekas

Han Hua Leong

Zhi Y Wong

Chiang Wei Lee

Albert Lee

Kia Leong Tan

Transceiver circuitry may include a storage element that receives data signals from an external element, an alignment detector circuit, and a register. The storage element has a write clock terminal that receives a channel clock signal and a read clock terminal that receives another channel clock signal. The alignment detector circuit is adapted to generate an asserted ready signal when a predefined pattern is detected in the received data signals. The register receives an output signal from the storage element and outputs the output signal based on the asserted ready signal that is generated by the alignment detector circuit. The register may be clocked by the same channel clock signal that is received at the read clock terminal of the storage element.

Methods and apparatus for aligning signals in transceiver circuitry

Circuits and techniques for operating an integrated circuit are disclosed. A disclosed method includes receiving a data packet with a first operating frequency rate with first and second receiver circuits. The data packet may include a plurality of preamble bits. The first and second receiver circuits may operate at second and third operating frequency rates, respectively. A portion of the data packet received at the first receiver circuit is transmitted to a control circuit. The plurality of preamble bits within the portion of the data packet is identified with the control circuit. A clock circuit is then calibrated based on the plurality of preamble bits. The first and second receiver circuits may be clocked with first and second clock outputs from the clock circuit.

Techniques for calibrating a clock signal

Techniques for sampling input data streams with an integrated circuit (IC) are provided. The technique includes receiving a first input stream at a first operating rate. The first input stream is transmitted to a plurality of subsequent transceiver channels on the IC. The first input stream is then sampled at a second operating rate at each of the plurality of subsequent transceiver channels with each of the plurality of subsequent transceiver channels outputting a data stream at the second operating rate. The data stream from each of the plurality of subsequent transceiver channels is adjusted. A data stream from one of the plurality of subsequent transceiver channels is selected as an output of the IC.

Techniques for oversampling a data stream in an integrated circuit

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Bayan Lepas, Malaysia

Keen Yew Loke