Samsung Electronics Co., Ltd.

KeeMoon Chun

Junho Kim

Seoungjae Yoo

Yuncheol Han

Byungki Moon

Myoungoh Ki

Jangbeom Yang

InChun Lim

Junho Song

Donghan Lee

Jin-han Kim

Yongkyu Lee

Yong Ki Lee

Boyoung Seo

Yong-Hun Kim

Yun-Ho Youm

Hajun Lee

Jinsu Hyun

Changhun Lee

Jaesop Kong

Hong-Mook Choi

SeongJong Yoo

Yeonwoo Jung

A bio-processor, a bio-signal detecting system, and an operation method of the bio-processor are provided. The bio-processor includes a bioelectrical impedance sensor and a digital signal processor. The bioelectrical impedance sensor measures bioelectrical impedance during a sensing time including a portion of a settling time. The digital signal processor estimates a settled bioelectrical impedance value based on changes in the measured bioelectrical impedance. The digital signal processor generates bio-data based on the settled bioelectrical impedance value. The bio-processor reduces a time when a bio-signal is measured and ensures accuracy of the settled bioelectrical impedance value.

Bio-processor, bio-signal detecting system, and operation method of bio-processor

A bio-processor includes a bioelectrical impedance sensor and a digital signal processor. The bioelectrical impedance sensor measures bioelectrical impedance during a sensing time including a portion of a settling time. The digital signal processor estimates a settled bioelectrical impedance value based on changes in the measured bioelectrical impedance. The digital signal processor generates bio-data based on the settled bioelectrical impedance value.

A source driver circuit is provided which includes a plurality of digital multi-spread (hereinafter referred to as 'DMS') blocks configured to generate DMS signals for controlling an output timing of a data signal to be transmitted to a display panel from a plurality of clocks which are delayed as much as a reference period one another. Each DMS block includes a plurality of sub blocks. Each of the sub blocks includes an enable signal generator and a delay unit. The enable signal generator generates an enable signal for outputting target DMS signals of the DMS signals using clocks selected from the plurality of clocks. The delay unit delays the DMS signals such that the DMS signals are sequentially delayed by the reference period.

Source driver and operating method thereof for controlling output timing of a data signal

A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.

Encoder and method for encoding thereof

A system-on-chip is provided which includes a data producer; a FIFO buffer which stores data transferred from the data producer at a memory area corresponding to a write pointer; a first consumer which pops data of a memory area corresponding to a first read pointer of the FIFO buffer out; and a second consumer which pops data of a memory area corresponding to a second read pointer of the FIFO buffer out. The FIFO buffer requests a pop-out operation at the second consumer according to the difference between the write pointer and the first read pointer or overwrites data provided from the data producer at a memory area corresponding to the second read pointer.

System-on-chip and application processor including FIFO buffer and mobile device comprising the same

The inventive concepts provide a semiconductor memory device including variable resistance memory elements. The semiconductor memory device may include a first bit line disposed at a first height from a semiconductor substrate, a second bit line disposed at a second height, which is different from the first height, from the semiconductor substrate, a first variable resistance memory element connected to the first bit line, and a second variable resistance memory element connected to the second bit line. The first and second variable resistance memory elements may be disposed at substantially the same height from the semiconductor substrate.

Semiconductor memory device

A method of forming a semiconductor device having a contact structure includes forming an insulating layer on a semiconductor substrate, and selectively implanting impurity ions into a predetermined region of the insulating layer to generate lattice defects in the predetermined region of the insulating layer. A thermal treatment, such as quenching the insulating layer at a temperature change rate of at least &#x2212;20&#xb0; C./minute, is performed on the insulating layer having the lattice defects to accelerate generation of the lattice defects in the predetermined region such that a conductive region results from the generated lattice defects to provide current paths in the predetermined region.

Methods of forming a semiconductor device having a contact structure

Growing community of inventors

Seongnam-si, South Korea

KeeMoon Chun