Qualcomm Incorporated

Keejong Kim

Chulmin Jung

Changho Jung

Sei Seung Yoon

Anil Chowdary Kota

Hochul Lee

Ritu Chaba

Fahad Ahmed

Arun Babu Pallerla

A memory is provided that is configured to practice both a conventional normal read operation and also a burst mode read operation. During the normal read operation, the memory pre-charges the bit lines in a group of multiplexed columns. Each column has a sense amplifier that latches a bit decision for the column during the normal read operation. If a subsequent read operation addresses the same group of multiplexed columns, the memory invokes the burst-mode read operation during which the bit lines are not pre-charged.

SRAM with burst mode operation

Certain aspects of the present disclosure provide methods and apparatus for testing a one-time programmable (OTP) memory device, including the functionality of a sense amplifier circuit. The OTP memory device includes a memory array, an input latch circuit, and a sense amplifier circuit comprising a current source and a multiplexer. The multiplexer has a first input coupled to an output of the memory array, a second input coupled to the input latch circuit, and an output coupled to an input of the current source circuit.

Testing one-time programmable (OTP) memory with data input capture through sense amplifier circuit

A One Time Programmable (OTP) memory, includes: a first driver coupled to a reference cell by a first bit line; a second driver coupled to an OTP cell by a second bit line; and a comparator having a first input coupled to the first bit line and the reference cell, a second input coupled to the second bit line and the OTP cell, and an output coupled to a logic circuit configured to control the first driver and the second driver.

Systems and methods to provide write termination for one time programmable memory cells

In certain aspects, a memory device includes memory bit cells coupled to a read bit line, and a first sense amplifier having a first input coupled to the read bit line, and a first output. The memory device also includes a latch amplifier having a first input coupled to the first output of the first sense amplifier, an enable input, and an output. The memory device also includes one or more dummy bit cells coupled to a dummy bit line, and a second sense amplifier having a first input coupled to the dummy bit line, and an output. The memory device further includes a trigger circuit having an input coupled to the output of the second sense amplifier, and an output coupled to the enable input of the latch amplifier.

Read tracking scheme for a memory device

A memory is provided that is configured to practice both a normal read operation and also a burst mode read operation. A burst mode address comparator compares a current row address to a previous row address to determine whether a read operation is a normal read operation or a burst mode read operation.

SRAM with burst mode address comparator

A memory includes a memory cell, one bitline coupled to the memory cell, a sense amplifier coupled to the one bitline, a timing circuit configured to enable the sense amplifier during a read operation, a control circuit configured to enable the sense amplifier independent of the timing circuit, and a pull-up circuit configured to pull up the one bitline while the sense amplifier is enabled by the control circuit. The method includes enabling a sense amplifier in a read operation by a timing circuit. The sense amplifier is coupled to at least one bitline, and the at least one bitline is coupled to a memory cell. The method further includes enabling the sense amplifier independent of the timing circuit in a second operation and pulling up the at least one bitline by a pull-up circuit while the sense amplifier is enabled in the second operation.

Timed sense amplifier circuits and methods in a semiconductor memory

A memory and a method for operating a memory are provided. The memory includes a memory cell having a first circuit to store a bit and a second circuit to decouple the stored bit from a power supply and from a return. The method includes storing a bit in a memory cell by a first circuit and decoupling the stored bit from a power supply and a return by a second circuit. Another memory is provided. The memory includes a memory cell having means for storing a bit by a feedback and means for disabling the feedback.

Memory cell with improved write margin

A memory and a method to operate the memory are provided. The memory includes a plurality of memory cells and a wordline driver configured to output a wordline. The memory cells are coupled to the wordline. A control circuit is configured to supply an operating voltage to the memory cells and to the wordline driver. A voltage-adjustment circuit is configured to adjust the operating voltage supplied to the memory cells during the control circuit supplying the operating voltage to the memory cells and to the wordline driver. The method includes supplying an operating voltage to at least one memory cells and to a wordline coupled to the at least one memory cells and adjusting the operating voltage supplied to the at least one memory cells during the supplying the operating voltage to the at least one memory cells and to the wordline.

Growing community of inventors

Phoenix, AZ, United States of America

Keejong Kim