Samsung Electronics Co., Ltd.

KeeHo Jung

Sangwan Nam

Sangyong Yoon

Sang-Hyun Joo

Hyunggon Kim

Suchang Jeon

Bongkil Jung

Chang-Wook Seo

A memory device includes a memory cell array having a plurality of cell blocks therein, including at least one cell block configured to store information data read (IDR) data related to setting an operating environment of the memory device. A setting data storage circuit is provided, which includes a plurality of storage regions in which the IDR data, which is read from the at least one cell block, is stored and a reset operation is independently controlled. Control logic is provided, which is configured to control at least one of a reset operation on the setting data storage circuit, and an IDR operation of updating the IDR data to the setting data storage circuit according to a decoding result of an external command. The control logic is configured to selectively reset only some storage regions of the setting data storage circuit in response to a determination that the external command is a first reset command, but reset all storage regions of the setting data storage circuit in response to a determination that the external command is a second reset command.

Memory devices that support selective setting data update and methods of operating same

A memory device includes a test mode detector circuit that determines whether the memory device has entered a test mode based on at least one test mode entry signal received through at least one pin of a plurality of pins and generates a test mode detection signal, and a test pad connection circuit that electrically couples a first pin of the plurality of pins to a dedicated test pad of the test mode such that a signal applied to the first pin is transmitted to the dedicated test pad based on the test mode detection signal.

Memory device including test pad connection circuit

Provided are a memory device detecting a defect and an operating method thereof. The memory device includes a memory cell area including a memory cell array that stores data, and a peripheral circuit area including a control logic configured to control operations of the memory cell array, wherein the peripheral circuit area further includes a defect detection circuit, the defect detection circuit being configured to generate a count result value by selecting a first input signal from a plurality of input signals and counting at least one time interval of the first input signal based on a clock signal, and to detect a defect of the first input signal by comparing an expected value with the count result value, and the at least one time interval is a length of time in which logic low or logic high is maintained.

Semiconductor memory device detecting defect, and operating method thereof

The memory device includes a page buffer circuit including a page buffer connected to each of a plurality of bit lines. The page buffer includes at least one additional latch and N number of data latches, and a control logic circuit that controls a setting of the page buffer. Based on a first setting, data programmed in a current program operation is stored in some of the N data latches and the at least one additional latch, and data which is to be programmed in a next program operation before the current program operation is completed is stored in some other of the N data latches and the at least one additional latches. Based on a second setting, externally provided data is not stored in the at least one additional latch in the current program operation and the next program operation.

Page buffer including latches and memory device including the page buffer

A nonvolatile memory device includes a memory cell array, a row decoder, and page buffer, and control logic. The memory cell array includes cell strings connected to select lines. Each select line is connected to two or more cell strings, each cell string includes memory cells connected to a plurality of word lines, and a select transistor is connected to a corresponding one of the select lines. The row decoder sequentially selects the select lines in a read operation. A page buffer obtains a read result of the two or more cell strings when a corresponding select line is selected and accumulates read results of the cell strings when the select lines are sequentially selected. The control logic controls a subsequent operation based on the accumulated read results.

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Suwon-si, South Korea

KeeHo Jung