Metisx Co., Ltd.

Xcena Inc.

Keebum Shin

Do Hun Kim

Kwangsun Lee

It is one object of the present disclosure to provide measures for securing scalability of the queue depth of cache schedulers by utilizing a plurality of cache schedulers. To this end, a cache memory device in accordance with one embodiment of the present disclosure comprises: a request reception unit configured to receive input transactions; a traffic monitoring module configured to monitor traffic of the input transactions; N cache schedulers, wherein N is an integer greater than or equal to 2; a region setting module configured to set N input transaction regions corresponding to each of the N cache schedulers based on the traffic of the input transactions monitored, wherein input transactions are transferred via an input transaction region set in each cache scheduler; and an access execution unit configured to perform cache memory accesses to input transactions scheduled by the N cache schedulers.

Cache memory device and method for implementing cache scheduling using same

A multiprocessor system may include a plurality of processors including a first processor and a second processor; a first cache memory corresponding to the first processor; a second cache memory corresponding to the first processor and the second processor and storing a plurality of cache lines; and a controller manages data stored in the second cache memory. The second cache memory includes at least one first cache line in which data is written by the first processor and at least one second cache line in which data is written by the second processor. The controller: receives a command associated with a data update from the first processor, and in response to the command, sets the first cache line as a clean cache line or an invalidated cache line while not setting the second cache line as a clean cache line or an invalidated cache line.

Multiprocessor system and data management method thereof

Provided is a cache memory device including a command reception unit for packetizing each of read commands and write commands and classifying them as even or odd; a cache scheduler comprising a first reorder scheduling queue for receiving commands classified as even numbers from the command reception unit and scheduling the commands classified as even numbers for cache memory accesses and a second reorder scheduling queue for receiving commands classified as odd numbers from the command reception unit and scheduling the commands classified as odd numbers for cache memory accesses; and an access execution unit for performing cache memory accesses via a cache tag to scheduled commands classified as even numbers and scheduled commands classified as odd numbers.

Growing community of inventors

Seongnam-si, South Korea

Keebum Shin