Electronics and Telecommunications Research Institute

Kee Wook Rim

Sang Man Moh

Jae Sung Lee

Young Woo Kim

Myung Joon Kim

Kyoung Ran Park

Suk Han Yoon

Sung Nam Kim

Woo Jong Hahn

Yong Youn Kim

Jong Seok Hahn

Sang Seok Shin

A device for effectively and economically receiving a packet by eliminating temporary memory and a memory controller. The apparatus includes an inspection logic circuit for inspecting data units as soon as they arrive in order to find an error included in the packet and generating control signals according to a result of inspecting a data unit; a multiplexer for receiving data units and distributing the received data units as soon as the data units have arrived; and FIFO memories for receiving the data unit, storing the data unit in a corresponding one of FIFO memories and either deleting or completing storing data units according to the control signals from the inspection logic circuit. The present invention can reduce manufacturing cost of the device by eliminating a temporary memory and a memory controller for the temporary memory and can also reduce processing time.

Apparatus for receiving data packet eliminating the need of a temporary memory and memory controller and method thereof

A routing switch for constructing an interconnection network of a parallel processing computer is disclosed. A purpose of the present invention is to provide a crossbar routing switch for a hierarchical interconnection network which has an expandability of a data length and an expandability of a hierarchical structure. The crossbar routing switch for a hierarchical interconnection network in accordance with the present invention comprises a predetermined number of input control units for controlling one input port to perform the manipulation of input data; a crossbar core unit for analyzing a data transmission request by the input control unit and outputting the corresponding data; and a predetermined number of output control unit for controlling one output port and receiving the output data from the crossbar core unit to output it to the output port. The present invention has advantages over the prior art that a data expandability can be provided by simply adding a routing switch without re-designing or re-manufacturing the routing switch several times, and that it can be suitably adapted to an interconnection network of a parallel processing system which requires a high expandability and high performance.

Crossbar routing switch for a hierarchical crossbar interconnection

The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.

Message transfer apparatus for controlling a message send in a packet

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Daejon-Shi, South Korea

Kee Wook Rim