Electronics and Telecommunications Research Institute

Kee-Wook Rim

Myung-Joon Kim

Kyoung Ran Park

Sang Man Moh

Jae Sung Lee

Youngwoo Kim

Yong Seok Choi

Joong-Bae Kim

Yong Youn Kim

Jong Seok Han

Jin-Pyo Kim

Won-Sae Sim

Jong-Seok Han

Woo-Jong Hahn

Yong-Yun Kim

The present invention is a data transfer protocol control system with a host bus interface that includes a transmitting/receiving command DMA, a transmitting data DMA and a receiving data DMA for controlling data transfer protocol with a host bus interface considering characteristic, usage frequency, simultaneous processing functions of the command DMA and the data DMAs. A host interface bus is efficiently used and bus usage ratio is distributed properly to support transfer flow properly and improve the entire system performance. The data transfer protocol control system with a host bus interface includes a transmitting/receiving command DMA for instructing the command DMA request buffer to read and write command message data, a transmitting data DMA for instructing the transmitting data DMA request buffer to read the command message data, a receiving data DMA for instructing the receiving data DMA request buffer to write the command message data and a data transfer protocol control device for putting read information, write information and message data on a host bus, receiving message data and a transfer response signal and delivering the message data through the response buffer of the corresponding DMA.

System for controlling data transfer protocol with a host bus interface

In a first-in first-out memory circuit using a standard cell library memory, a memory block includes N number of memories (N&#x3e;1). A read pointer designates read addresses of the N number of memories. A write pointer designates write addresses of the N number of memories. A memory controller selects one from the N number of memories based on the read/write addresses, generates n number of read/write clock signals by demultiplying a clock signal by n (n=N, n&#x3e;1) and sends the n number of read/write clock signals having a 1/n cycle difference to the N number of memories thereby inputting/outputting data.

First-in first-out memory circuit and method for executing same

The present invention relates to a hierarchical crossbar inter-connection network for a cluster-based parallel processing computer. A crossbar network is composed of the 'n' number of crossbar switches which is byte sliced, eight links for connecting eight nodes, and two links for connecting other clusters. In addition, one low-level cluster is formed by connecting a maximum of eight processing nodes between the two crossbar networks, and one high-level cluster is formed with a maximum of eight low-level clusters and the four crossbar networks. Moreover, one next high-level clusters formed with a maximum of eight high-level clusters and the eight crossbar networks for scalability.

Hierarchical crossbar interconnection network for a cluster-based

A VRAM-based parity engine for use in a disk array controller is disclosed, in which the parity arithmetic operation is carried out in a fast and effective manner, thereby improving the performance of the RAID system. Particularly, the parity data arithmetic operation is not resorted to a processor, but to a VRAM, thereby realizing a high speed operation. In the disk array controller, a VRAM (video RAM) is used, in such a manner that the reading, updating and writing are made to be overlapped during the arithmetic operation, thereby promoting the speed of the arithmetic. Therefore, a relatively large capacity memory can be formed compared with the conventional SRAM, and therefore, a temporary buffer memory within the parity engine is used as a parity cache, thereby doubling the performance.

VRAM-based parity engine for use in disk array controller

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Kyonggido Kwangju, South Korea

Kee-Wook Rim