Samsung Electronics Co., Ltd.

Kee-wook Jung

Chang-sik Yoo

Won-chan Kim

Young-Don Choi

Dong-yun Lee

Yeon-jae Jung

Yi-do Koo

Joon-young Park

An output driver supplying constant output current regardless of output voltage changes. The output driver includes a current source for regulating changes in a voltage of an output terminal responsive to a reference signal, and an output current compensator that responds to the current source to supply constant current to the terminal. The current source includes a first MOS transistor having a drain coupled to the terminal and a gate to which the reference signal is input, and a second MOS transistor having a drain coupled to a source of the first MOS transistor, a gate to which data is input, and a source coupled to ground. The current source may be an open drain current source. The output current compensator includes a current compensator coupled to the terminal, and a sensing driver for sensing voltage changes of the terminal and driving the current compensator.

Output driver having output current compensation and method of compensating output current

A duty cycle correction circuit includes a duty cycle corrector and a detection circuit. The duty cycle corrector generates a first input signal having a second duty cycle with a higher degree of equivalence than the first duty cycle in response to a first detection signal and a first control signal having a first duty cycle. The detection circuit generates the first detection signal in response to the first input signal. The detection circuit includes a current source having first and second current sources and a bias circuit that is electrically coupled to the first and second current sources and controls a bias of the first and the second current sources responsive to the first input signal.

Duty cycle correction circuits that reduce distortion caused by mismatched transistor pairs

A ladder type clock network for reducing the skew of clock signals is provided. The clock network includes a buffer for buffering a clock signal, first delay units for delaying the output of the first buffer by a set time, second buffers connected to respective outputs of the first delay units, and second delay units connected to respective outputs of the second buffers. The first delay units and the second delay units consist essentially of the resistance and capacitance of lines through which the clock signal propagates. Accordingly, the skew of the internal clock signals is reduced, and internal clock signals having a stable duty with respect to variations in a semiconductor device manufacturing process, temperature, and power supply voltage, are generated.

Ladder type clock network for reducing skew of clock signals

An input buffer circuit for transforming pseudo differential input signals into full differential output signals wherein, the input buffer circuit includes a pull-up current source, two pull-down current sources, a differential input portion, and a positive feedback portion. The pull-up current source is formed of two PMOS transistors which are always in an &ldquo;on&rdquo; state, and provides an electric current. The two pull-down current sources are each formed of an NMOS transistor, which are always in an on state, and sink a pull-up electric current. The differential input portion is formed of two NMOS transistors, and receives an input signal and a reference signal, respectively. The positive feedback portion is formed of two NMOS transistors, and enlarges a voltage difference between two output terminals of the input circuit using positive feedback.

Input buffer circuit for transforming pseudo differential signals into full differential signals

An integrated circuit having a locking circuit and method using the same are provided. The locking circuit includes a time-to-digital converter. The time-to-digital converter includes first and second delay chains, each for delaying one of two input signals at predetermined intervals. The time-to-digital converter also includes first and second phase comparators, each for comparing the delayed signal with the other signal and generating a digital signal. The locking circuit converts the phase difference between a feedback signal and an internal clock signal into a delay control signal group using the time-to-digital converter. The delay control signal group controls the delay time of a mirror delay circuit to rapidly minimize the phase difference between the feedback signal and the internal clock signal.

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Seoul, South Korea

Kee-wook Jung