Samsung Electronics Co., Ltd.

Sungkyunkwan University

Kee-Won Kwon

Chang-jung Kim

Young-soo Park

Sang-Wook Kim

I-hun Song

Sun-il Kim

Seok Hwan Kim

Jae-Chul Park

Chan-Kyung Kim

Cheol Su Kim

Junhan Bae

Youngsoo Sohn

Jung Hoon Chun

Sung-Gi Ahn

Rak-Joo Sung

Yoon-Dong Park

Jung-Hwan Choi

Chul-woo Park

Seung-hoon Lee

Young-Soo Park

Uk-Song Kang

Jae-woong Hyun

Sung-ho Park

Jae-Youn Youn

Sung-hoon Lee

Hoon Shung Lee

Su-a Kim

Kyoung-Lae Cho

Kyoung-kook Kim

Seung-Hoon Lee

Kyungho Kim

Kyoungho Kim

Ju-hee Park

Duk-Min Kwon

Hyun-Suk Kang

Ji-Su Min

Byung-Kwan Chun

Youn-Cheol Kim

Chang-Jung Kim

A ternary content addressable memory (TCAM) device includes a memory cell. The memory cell includes a data storage circuit, a limiter circuit, and a discharge circuit. The data storage circuit includes a first resistor and a second resistor connected in series to divide a voltage corresponding to search data, and configured to store cell data. The limiter circuit is configured to receive the divided voltage through an input terminal and transmit an output voltage through an output terminal based on a level of the divided voltage. The discharge circuit discharges a matching line indicating whether the stored cell data matches with the search data, based on the output voltage of the limiter circuit.

TCAM device and operating method thereof

A memory device includes a storage circuit, a first driving circuit, and a second driving circuit. The storage circuit stores first data and compares the first data and second data. The first driving circuit selectively drives a matching line to a first logic state, depending on a comparison result of the first data and the second data by the storage circuit. The second driving circuit drives the matching line to a second logic state regardless of the comparison result.

Memory device driving matching lines according to priority

A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

On-chip resistance measurement circuit and resistive memory device including the same

A phase-rotating phase locked loop (PLL) may include first and second loops that share a loop filter and a voltage controlled oscillator in order to perform the operation of a phase-rotating PLL, the first and second loops configured to activate in response to an enable signal. The PLL may further include a phase frequency detection controller configured to provide the enable signal to the first and second loops in response to a transition of a coarse signal that may be applied as a digital code.

Phase-rotating phase locked loop and method of controlling operation thereof

A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

Memory cores of resistive type memory devices, resistive type memory devices and method of sensing data in the same

A stacked memory device includes a plurality of memory layers, where at least one of the plurality of memory layers is stacked on another of the plurality of memory layers and each of the memory layers includes an array of memory cells, a first active circuit unit configured to classify and process address information for at least one of the memory cells as vertical address information and horizontal address information, and at least one second active circuit unit configured to generate a memory selection signal for at least one of the memory cells based on signals processed by the first active circuit unit.

Stacked memory device and method thereof

Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device may be a complementary device including a p-type oxide TFT and an n-type oxide TFT. The semiconductor device may be a logic device such as an inverter, a NAND device, or a NOR device.

Semiconductor devices and methods of fabricating the same

Provided are a semiconductor device having a block state confirmation cell that may store information indicating the number of data bits written to a plurality of memory cells, a method of reading memory data based on the number of the data bits written, and/or a memory programming method of storing the information indicating the number of the data bits written. The semiconductor device may include one or more memory blocks and a controller. Each of the memory blocks may include a plurality of memory cells each storing data, and a block state confirmation cell storing information indicating the number of data bits written to the memory cells. The controller may read the data bits from the memory blocks based on the number of data bits, which is indicated in the information in the block state confirmation cell.

Non-volatile memory device including block state confirmation cell and method of operating the same

A self-calibrating temperature sensor and a method thereof are provided. The self-calibrating temperature sensor may include a reference voltage generator to generate a reference voltage based on temperature, a digital-to-analog converter to convert a first digital signal into an analog sensing voltage, a comparator to compare the reference voltage with the analog sensing voltage, and to generate a comparison result signal, a digital signal generator to generate and update the first digital signal based on the comparison result signal, a first storage circuit to store the first digital signal based on a first temperature, a data output unit to output data corresponding to a second temperature based on the first digital signal and a second digital signal output from the first storage circuit.

Self-calibrating temperature sensors and methods thereof

A dynamic random access memory device having reduced power consumption and a refresh cycle method. The memory device includes a monitoring address storage unit storing multiple monitoring addresses, an error correction code (ECC) engine detecting whether or not an error occurs in monitoring bits corresponding to the monitoring addresses, and a refresh cycle determining circuit adjusting a self refresh cycle depending on whether or not an error occurs in the monitoring bits.

Dynamic random access memory device and associated refresh cycle

A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the global input/output line pair. The detect control signal generating unit disables an operation of the sense amplifier and precharges the global input/output line pair to a predetermined voltage. A precharge operation of a memory device may be performed at a higher speed so that a high speed operation of the memory device may be achieved. In addition, the operating time of the sense amplifier may be decreased so that the power consumption of the memory device may be reduced.

Memory device and method of operating the same

A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data received through a data bus to the first port in response to a leading edge of a clock signal and assigns second data received through the data bus to the second port in response to a trailing edge of the clock. Methods of operating memory devices having a dual port mode are also disclosed.

Semiconductor memory devices having a dual port mode and methods of operating the same

An output driver is responsive to an input signal and a swing width control signal (TE). The output driver is configured to generate an output signal having a first swing width (e.g., less than rail-to-rail) when the swing width control signal designates a normal mode of operation and a second swing width (e.g., rail-to-rail) when the swing width control signal designates a test mode of operation.

Output drivers having adjustable swing widths during test mode operation

A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

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Seongnam-si, South Korea

Kee-Won Kwon