Hynix Semiconductor Inc.

Kee-Teok Park

Chun-Seok Jeong

Jae-Hyuk Im

Ji-Eun Jang

Ki-Ho Kim

Sun-Hyuck Yon

Sang-Jin Byeon

Young-Jun Ku

Tae-Sik Yun

A semiconductor memory device includes a clock synchronizing unit for receiving a first power voltage through a first power voltage terminal, and an additional power voltage providing unit for additionally providing a second power voltage to the first power voltage terminal for a predetermined period after leaving a power down mode.

Semiconductor memory device and operation method thereof

An on die thermal sensor (ODTS) for use in a semiconductor device includes a temperature information output unit for measuring an internal temperature of the semiconductor device to generate a temperature information code having temperature information, and updating the temperature information code according to a refresh period.

On die thermal sensor

An on die thermal sensor (ODTS) for use in a semiconductor memory device includes: a temperature information code generation unit for sensing an internal temperature of the semiconductor memory device in response to first and second enable signals and for generating a temperature information code which includes the sensed temperature information; and a flag signal logic determination unit for generating a plurality of first flag signals having temperature information and determining whether the plurality of first flag signals have a predetermined logic level or a variable logic level in response to the first and second enable signals.

A semiconductor memory device performs a refresh operation stably even while a temperature continuously changes at near a specific temperature. The semiconductor memory device includes an on die thermal sensor (ODTS) and a control signal generator. The on die thermal sensor (ODTS) outputs a thermal code corresponding to a temperature of the semiconductor memory device. The control signal generator generates a self refresh control signal in response to the thermal code, wherein a state of the self refresh control signal does not change when the temperature variation is less than a predetermined value.

Semiconductor memory device and method for driving the same

Semiconductor device and data outputting method of the same includes an on die thermal sensor (ODTS) configured to output temperature information by detecting an internal temperature of the semiconductor device and an output driver configured to control a slew rate depending on the temperature information and output data.

Semiconductor device and data outputting method of the same

A semiconductor memory device for measuring a data access time by controlling data output operation, including: a pipe latch control unit for generating an input control signal based on a test mode signal; a pipe latch unit for receiving data and controlling the data according to a CAS latency in synchronization with a clock signal at a normal mode or passing the data without synchronization with the clock signal at a test mode based on the input control signal; an output control unit for generating an output node control signal based on the test mode signal; and an output unit for controlling an output data outputted from the pipe latch means according to the CAS latency in synchronization with the clock signal at the normal mode or passing the output data without synchronization with the clock signal at the test mode based on the output node control signal.

Semiconductor memory device having test mode for data access time

An impedance matching circuit performs a ZQ calibration for a test on a wafer process of a semiconductor memory device. The impedance matching circuit of the semiconductor memory device includes a first pull-down resistance unit, a first pull-up resistance unit, a second pull-up resistance unit and a second pull-down resistance unit. The first pull-down resistance unit supplies a ground voltage to a first node in response to a calibration test signal. The first pull-up resistance unit calibrates its resistance to that of the first pull-down resistance unit to thereby generate a pull-up calibration code. The second pull-up resistance unit supplies a supply voltage to a second node in response to the pull-up calibration code. The second pull-down resistance unit calibrates its resistance to that of the second pull-up resistance unit to thereby generate a pull-down calibration code.

Impedance matching circuit and semiconductor memory device with the same

Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device, including a pre-driver to generate a pull-up control signal and a pull-down control signal according to a logic value of data to output, and to adjust and output a slew rate of the pull-up control signal and a slew rate of the pull-down control signal according to a termination resistance setting information, a pull-up driver to output logic high data in response to the pull-up control signal and a pull-down driver to output logic low data in response to the pull-down control signal.

Output driver circuit, semiconductor memory device including the output driver circuit, and method for operating the semiconductor memory device

A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. The first signal generator generates a pre-calibration signal during an initialization of the semiconductor memory device. The second signal generator generates ZQ calibration signals in response to a ZQ calibration command. The control unit outputs signals to control a ZQ calibration in response to the pre-calibration signal and the ZQ calibration signals.

ZQ calibration controller and method for ZQ calibration

A semiconductor memory device is capable of performing a normal operation, while detecting an internal voltage without a special bonding method during a test mode. The semiconductor memory device comprises a switching unit and an internal reference voltage generating unit. The switching unit transfers one of an internal and an external reference voltages according to whether a test mode is being performed, wherein the external reference voltage is input from outside of the semiconductor memory device. The internal reference voltage generating unit generates the internal reference voltage having the same level of the external reference voltage to thereby supply the internal reference inside the semiconductor memory device during the test mode.

Test circuit for semiconductor memory device

A test circuit in a memory device includes a first compression unit configured to compress data of a plurality of cells to transmit first compressed data to a plurality of input/output lines, and a second compression unit configured to compress the first compressed data on the plurality of input/output line to output second compressed data to at least one output pin, wherein the second compression unit operates in a low compressing mode and a high compressing mode in response to a data compression selecting signal.

Circuit and method for parallel test of memory device

Provided is a test mode control circuit capable of preventing an MRS (mode register set) from changing in a test mode exit after a test mode entry. In the test mode control circuit, an MRS controller logically combines an MRS signal, a bank address, an MRS address, and a test mode control signal to output a latch control signal. A test mode control unit detects a test mode entry and a test mode exit to selectively activate one of a test mode set signal and a test mode exit signal, and outputs the test mode control signal having different voltage levels according to an activation state of the test mode set signal or the test mode exit signal. An address latch latches an input address when the MRS signal is activated, and outputs the latched input address as the MRS address when the latch control signal is activated.

Test mode control circuit

A semiconductor memory device performs a reset operation at a wafer state by using a signal input through an address pin in a test mode. The semiconductor memory device includes a buffer for transferring a reset command in response to a reset-active signal and a test reset signal, a test-reset entry signal generation unit for generating an internal test-reset entry signal in response to the test reset signal, and a rest signal driving unit for driving an active signal of an output signal of the buffer and the internal test-reset entry signal as an internal reset signal for a reset mode entry.

Semiconductor memory device with reset during a test mode

A semiconductor memory device includes: a temperature information output unit for measuring an internal temperature of the semiconductor memory device, and generating a plurality of flag signals, each voltage level of which varies according to the measured internal temperature; a self-refresh oscillation unit for providing a self-refresh period corresponding to the measured internal temperature in response to the plurality of flag signals; and a temperature information control unit for determining a measuring period of the temperature information output unit in response to a temperature sensing enable signal and the plurality of flag signals.

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Kyoungki-do, South Korea

Kee-Teok Park