Intel Corporation

Other

Synopsys, Inc.

Kee Sup Kim

Subhasish Mitra

Ming Lei Zhang

Tak Ming Mak

Quan Shi

Rathish Jayabharathi

Ajith Prasad

Prashant M Goteti

Leonard J Schultz

Shyang-Tai Sean Su

Avi Kovacs

Adarsh Kalliat

Saviz Artang

Techniques for providing improved semiconductor yield learning are discussed herein. Some embodiments may include a yield learning vehicle (YLV), including a communication fabric and a plurality of circuit blocks connected with the communication fabric. The plurality of circuit blocks may include circuit blocks having different design window sizes, and may be configured to support different phases of a yield learning ramp up process. The YLV may further include a yield learning controller configured to control circuit block testing, and bypasses configured to partially or fully replicate the behavior of improperly functioning or untested circuit blocks. Some embodiments may include techniques for software implementation of the YLV, such as by invoking a computer to receive data representative of a design of the YLV, and based on the data representative of the design of the integrated circuit, causing the computer to generate data representative of YLV.

Logic yield learning vehicle with phased design windows

In one embodiment, the present invention includes first level matrices, each including m input terminals and n output terminals, each coupled to a processor core, and second level matrices each coupled to the n output terminals of one of the first level matrices, where each of the second level matrices has n input terminals and p output terminals, and the p output terminals of the second level matrices correspond to a compacted output from the multiple processor cores. Other embodiments are described and claimed.

Hierarchical test response compaction for a plurality of logic blocks

Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

Compacting circuit responses

A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.

In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.

System and shadow bistable circuits coupled to output joining circuit

In one embodiment, an apparatus includes a system circuit adapted to generate at a first output terminal a first output signal in response to a data input signal and at least one system clock signal; a shadow circuit adapted to generate at a second output terminal a second output signal in response the data input signal and the at least one system clock signal; and an output joining circuit coupled to at least the first output terminal and the second output terminal.

System and shadow circuits with output joining circuit

In one embodiment, a method is provided. In the method of this embodiment, a stimulus signal set may be generated and supplied, as input, to first circuitry. Each respective stimulus signal in the stimulus signal set may be generated based at least in part upon a respective non-null subset of an input signal set. No two respective stimulus signals in the stimulus signal set may be generated based upon the same respective non-null subset of the input signal set. The stimulus signal set may include a respective number of stimulus signals that is greater than a respective number of input signals in the input signal set. Of course, many modifications, variations, and alternatives are possible without departing from the method of this embodiment.

Stimulus generation

In one embodiment, an apparatus includes a datapath circuit to generate a data output signal in response to a data input signal and at least a first data clock signal; a shadow circuit, coupled to the datapath circuit, to generate a shadow output signal in response the data input signal and at least a second data clock signal during a functional mode of operation and to generate a scan-out signal in response to a scan-in signal and at least a first test clock signal during a test mode of operation; and an error detect circuit, coupled to the datapath and the shadow circuits, to generate an error signal in response to a mismatch between the data output signal and the shadow output signal.

Error detecting circuit

A testing device uses an input signature register to conduct 'at speed' testing of asynchronous circuit responses in an effort to determine the operability of a monitored circuit. Upon receiving an enable signal, the input signature register quickly measures, compresses, and transmits the tested circuit responses so that the responses can be compared with a set of anticipated responses to determine whether the circuit is functioning properly. The enabled input signature register, such as a MISR or a SISR, generates an output signature, which contains the compressed responses of the monitored circuit and helps the testing device analyze circuit performance.

At speed testing asynchronous signals

A tractable architecture level coverage measure uses information about the coverage measures obtained by the data path blocks, control logic blocks and cache to obtain an overall measure of coverage. This technique is applicable to a variety of different designs using different fabrication processes. Moreover, it allows the use of extended length test vectors, for example, such as those using commercial software applications. Since the coverage measure does not rely on the traditional stuck at model, it is applicable to extended length test vectors that may be used with high performance systems.

Architectural coverage measure

A scan chain and method of generating non-successive pseudo-random test patterns for performing a built-in self test (BIST) on a circuit block in an integrated circuit. The scan chain includes a linear feedback shift register (LFSR) cascaded with a shift register. An output of a last storage element of the shift register is fed back in to an input of a first storage element of the LFSR such that the shift register and LFSR form a circular path. A first test pattern is generated in the scan chain when a data string stored in the shift register is shifted through the LFSR. The test pattern is then asserted on inputs of the circuit block. The circuit response is stored in the scan chain, and the scan chain is shifted once more in order to compress the result and generate a second test pattern simultaneously.

Scan-based built-in self test (BIST) with automatic reseeding of pattern

A scan chain for testing sequential logic circuitry includes a number of concatenated storage elements having a feedback loop from the output of the last storage element to the input of the first storage element. The storage elements are clocked by a chain clock signal at a frequency multiple of a base frequency. The number of storage elements in the scan chain is a relative prime with respect to the frequency multiple. Scan chains running at different frequency multiples of the base frequency may be concatenated with the output of the last storage element of one scan chain being coupled to the input of the first storage element of the next scan chain. Wherever the output of a storage element clocked on a leading phase of the chain clock signal is coupled to the input of a storage element clocked on a trailing phase of the chain clock signal, a buffer is inserted to buffer the output to the input.

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El Dorado Hills, CA, United States of America

Kee Sup Kim