Samsung Electronics Co., Ltd.

Kee-Moon Chun

Jae-hyun Yoo

Dong-Han Lee

Jae-Sop Kong

Jin-Hyun Noh

Seung-Hwan Baek

Hyuck-Jun Cho

Donald Na

Jae-Keun Oh

Hee-Seog Jeon

Jung-Hyun Cho

Yong-kyu Lee

Yong-Woo Jeon

Jae-Hong Ko

Jae-Suk Yu

Kwan-young Kim

Bo-young Seo

June-Taeg Lee

Jun-Ho Huh

Jong-Sung Jeon

Do-youn Kim

Jun-Suk Kim

Sung-Chul Yoon

Ji-Myung Na

Sung-Hoo Choi

Sun-Wook Heo

Sang-Ho Seo

Eun-Ji Kang

Choong-Jae Lee

Ho-hak Rho

A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.

Smart card device, system including the same and method of operating smart card system

An apparatus, method, chipset, and non-transitory computer-readable storage medium for controlling power are provided. The apparatus includes a receiver configured to receive a data frame and first information related to a next data frame of the data frame; and a controller configured to determine an operation mode as an active mode or a sleep mode based on destination address information of the next data frame and duration information indicating a time during which transmission of the next data frame occurs, wherein the destination address information and the duration information are included in the first information.

Apparatus and method for controlling power

A semiconductor device includes a first well disposed in a substrate and including a first impurity of a first conductivity type, a second well disposed in the substrate, including a second impurity of a second conductivity type different from the first conductivity type, and having first to third portions, and a gate structure formed on the first well and the second well, wherein the second portion is disposed between the first portion and the third portion, the first portion and the third portion are formed deeper than the second portion, and concentration of the second impurity of the first portion and the third portion is greater than concentration of the second impurity of the second portion.

Semiconductor device having a drift region with non-uniform impurity concentration profile

A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

Semiconductor device

A semiconductor device including an electrostatic discharge (ESD) protection circuit includes an input port, a logic circuit receiving an input signal applied to the input port and generating an output signal based on the input signal, and an ESD protection circuit adjusting a level of the input signal when the level of the input signal exceeds a predetermined range. The ESD protection circuit includes a first fin and a second fin arranged on a semiconductor substrate in parallel, and a gate electrode formed in a direction crossing the first fin and the second fin, each of the first fin and the second fin includes a source region, a drain region, and a channel region disposed between the source region and the drain region, the channel region is disposed under the gate electrode, a source region of the first fin and a drain region of the second fin are disposed at a first side of the gate electrode, and a drain region of the first fin and a source region of the second fin are disposed at a second side of the gate electrode.

Semiconductor device including ESD protection circuit

Method of operating smart card and method of operating smart card system including the same

A system-on-chip (SoC) includes a slave intellectual property (IP) block, a master IP block, and an update control unit. The slave IP block is configured to perform first processing on first data based on first control information stored in a first storage unit. The master IP block is configured to perform second processing on second data in response to receiving a first processing result obtained by performing the first processing on the first data. Performing the second processing is based on second control information stored in a second storage unit. The update control unit is configured to determine an update time of the first control information or an update time of the second control information in response to performing the first processing and performing the second processing.

System-on-chip and method of operating the same

A security circuit may include a functional circuit including a test chain that connects flip-flops to verify hardware of the functional circuit, the functional circuit configured to generate an output signal by encrypting an input signal based on a control signal, a mode signal, and the chain; and/or a test controller configured to generate the input, control, and mode signals, and configured to generate an authentication result based on the output signal. A security circuit may include a first device including a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second and third signals and the chain; and/or a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal.

Security circuits and security systems including the same

Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

System-on-chip having special function register and operating method thereof

A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

Magnetic memory devices including shared lines

Methods of forming semiconductor devices are provided. A method of forming a semiconductor device includes forming preliminary trenches adjacent opposing sides of an active region. The method includes forming etching selection regions in portions of the active region that are exposed after forming the preliminary trenches. The method includes forming trenches by removing the etching selection regions. Moreover, the method includes forming a stressor in the trenches. Related apparatuses are also provided.

Methods of forming semiconductor devices including an embedded stressor, and related apparatuses

Provided are a method of driving a liquid crystal panel which prevents unintended digital image data from being displayed on a liquid crystal panel when power is provided or interrupted, and a source driver and a liquid crystal display apparatus. The source driver includes output buffers; output pads; and a switching unit which is disposed between the output buffers and the output pads and controls an electrical connection state of the output pads. If a level up or a level down of a power voltage occurs, the switching unit prevents output signals of the output buffers from being transmitted to the liquid crystal panel via corresponding output pads and performs at least one of a charge sharing operation for connecting the output pads to each other and a discharging operation for providing a discharge path from the output pads to a ground terminal, in a preset period.

Liquid crystal panel driving method, and source driver and liquid crystal display apparatus using the method

An image sensor includes an array of image sensor cells, on a substrate, and a peripheral circuit region extending adjacent the array of image sensor cells. The array of image sensor cells includes a plurality of lens elements and a plurality of color filters extending adjacent the plurality of lens elements. A plurality of photodiodes is provided in the substrate. The plurality of photodiodes are aligned to corresponding ones of the plurality of lens elements. An interconnection structure is also provided, which extends between the plurality of photodiodes and the plurality of color filters. The interconnection structure has an array of cavities therein that are aligned to corresponding ones of the plurality of photodiodes and are filled with a light guide material. The peripheral circuit region includes a metal interconnect pattern and an electrically conductive pad on the metal interconnect pattern. An electrically insulating layer extends on the electrically conductive pad. The electrically insulating layer is formed of the light guide material.

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Seongnam-si, South Korea

Kee-Moon Chun