Hynix Semiconductor Inc.

Skhynix Inc.

Kee-Jeung Lee

Deok-Sin Kil

Jin-Hyock Kim

Young-Dae Kim

Kwan-Woo Do

Kyung-Woong Park

Jae-Sung Roh

Jeong-Yeop Lee

Han-Sang Song

Seung-Jin Yeom

Wan-Gee Kim

Jae-Min Lee

Sang-Do Lee

Jong-Bum Park

Jun-Soo Jang

Dong-Su Park

Beom-Yong Kim

Ji-Hoon Ahn

Hyung-Dong Lee

Kwon Hong

Woo-Young Park

Hyo-June Kim

Min-Soo Kim

Ki-Seon Park

Yun-Hyuck Ji

Seung-Mi Lee

Eun-Shil Park

Byung-Seop Hong

Yong-Seok Eun

Jong-Hyuk Oh

Jae-Hyoung Koo

Mi-Hyoung Lee

Ja-Yong Kim

Hong Kwon

A method for fabricating a semiconductor device includes: forming a mold stack pattern including a plurality of openings in an upper portion of a substrate and including a mold layer and a supporter layer which are stacked; forming a bottom electrode layer filling the plurality of the openings and covering the supporter layer; forming a filler portion disposed inside the plurality of the openings, a barrier portion extended upwardly from the filler portion, and an electrode cutting portion exposing a surface of the supporter layer by selectively etching the bottom electrode layer; forming a supporter by using the barrier portion as an etch barrier and etching the supporter layer exposed by the electrode cutting portion; selectively removing the barrier portion to form a hybrid pillar-type bottom electrode disposed inside the plurality of the openings; and removing the mold layer.

Semiconductor device and method for fabricating the same

An electronic device includes a semiconductor memory. The semiconductor memory includes a plurality of first lines extending in a first direction, a plurality of second lines extending in a second direction crossing the first direction, a resistance variable layer interposed between the first lines and the second lines, a tunnel barrier layer interposed between the resistance variable layer and the first lines, and an intermediate electrode layer interposed between the resistance variable layer and the tunnel barrier layer. The tunnel barrier layer and the intermediate electrode layer overlap with at least two neighboring intersection regions of the first lines and the second lines.

Memory device having a tunnel barrier layer in a memory cell, and electronic device including the same

A semiconductor device includes a first conductive layer, a second conductive layer spaced from the first conductive layer, a variable resistance layer interposed between the first and second conductive layers, and an impurity-doped layer provided over a side surface of the variable resistance layer. The variable resistance layer has a smaller width than the first and the second conductive layers.

Semiconductor device and electronic device including the same

An electronic device includes a switch element. The switch element includes a first electrode including a first metal nitride which is conductive, a second electrode, a switching layer interposed between the first electrode and the second electrode, and a first barrier layer which is interposed between the first electrode and the switching layer and includes a second metal nitride which is insulative, wherein a metal in the first metal nitride is the same as a metal in the second metal nitride, and a metal-to-nitrogen bonding ratio of the first metal nitride is different from a metal-to-nitrogen bonding ratio of the second metal nitride.

Electronic device including a switch element in which a metal nitride layer has a nitrogen concentration increasing as a closer distance from a switching layer, and method for fabricating the same

A semiconductor device includes a dielectric layer in which zirconium, hafnium, and a IV group element are mixed. A method for fabricating a capacitor includes forming a bottom electrode, forming the dielectric layer and forming a top electrode over the dielectric layer.

Method for fabricating semiconductor device

A method for fabricating a capacitor includes: forming a first silicon layer over a semiconductor substrate, where the first silicon layer is doped with a dopant; forming an undoped second silicon layer over the first silicon layer; forming an opening by etching the second silicon layer and the first silicon layer; forming a storage node in the opening; and removing the first silicon layer and the second silicon layer.

Method for fabricating capacitor with high aspect ratio

A method for fabricating a variable resistance memory device includes forming an oxygen-deficient first metal oxide layer over a first electrode, forming an oxygen-rich second metal oxide layer over the first metal oxide layer, treating the first and second metal oxide layers with hydrogen-containing plasma, forming an oxygen-rich third metal oxide layer, and forming a second electrode over the third metal oxide layer.

Variable resistance memory device and method for fabricating the same

A capacitor includes a pillar-type storage node, a supporter disposed entirely within an inner empty crevice of the storage node, a conductive capping layer over the supporter and contacting the storage node so as to seal an entrance to the inner empty crevice, a dielectric layer over the storage node, and a plate node over the dielectric layer.

Capacitor with pillar type storage node and method for fabricating the same

Growing community of inventors

Ichon-shi, South Korea

Kee-Jeung Lee